• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.3
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• pp.343-348
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• 2014

Recently, applications of VSC-HVDC systems to power systems are growing because of their control ability of reactive power. Meanwhile, the hardware-in-the-loop simulation (HILS) based on the real-time digital simulator has been applying to develop and test imbedded controllers and systems in the power industry to decrease costs and to save time. In this paper, a 3-level neutral point clamped (NPC) VSC-HVDC system is modeled and the embedded controllers of the NPC VSC-HVDC system are designed. The designed controllers are implemented by TMS320F28335. The TMS320F28335-based controllers of the NPC VSC-HVDC system are tested using the HILS.

• Journal of Power Electronics
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• v.17 no.2
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• pp.346-357
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• 2017

The Modular Multilevel Converter (MMC) is particularly attractive for medium and high power applications such as High-Voltage Direct Current (HVDC) systems. In order to reach a high voltage, the number of cascaded submodules (SMs) is generally very large. Thus, in the applications with hundreds or even thousands of SMs such as MMC-HVDCs, the sorting algorithm of the conventional voltage balancing strategy is extremely slow. This complicates the controller design and increases the hardware cost tremendously. This paper presents a Two-Way Merge Sort (TWMS) strategy based on the prediction of the capacitor voltages under ideal conditions. It also proposes an innovative Insertion Sort Correction for the TWMS (ISC-TWMS) to solve issues in practical engineering under non-ideal conditions. The proposed sorting methods are combined with the features of the MMC-HVDC control strategy, which significantly accelerates the sorting process and reduces the implementation efforts. In comparison with the commonly used quicksort algorithm, it saves at least two-thirds of the sorting execution time in one arm with 100 SMs, and saves more with a higher number of SMs. A 501-level MMC-HVDC simulation model in PSCAD/EMTDC has been built to verify the validity of the proposed strategies. The fast speed and high efficiency of the algorithms are demonstrated by experiments with a DSP controller (TMS320F28335).