• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.520-522
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• 1996

The Direct Drive Arm(DDA) is a SCARA typed direct drive manipulator with two degrees-of-freedom(DOF) using the direct drive motor of the NSK company. A controller system for the SCARA robot of DDA is designed using a DSP (TMS32Oc3O), which has the highest performance among the third DSP chips in the TI company. The design objective of the system is to implement dynamic control algorithms and neural control algorithms for real time learning which require a lot of calculations and large memory and have been tested only by simulations so far. The controller uses a DSP, a high speed D/A, 32-bit Counter and a large DRAM to implement advanced robot control algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9C
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• pp.1337-1344
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• 2004

This paper deals with analysis and real-time Implementation of a wide band adaptive multirate speech codec (AMR-WB) using a fixed-point DSP of TI's TMS320C6201. In the AMR-WB codec, input speech is divided into two frequency bands, lower and upper bands, and processed independently. The lower band signal is encoded based on the ACELP algorithm and the upper band signal is processed using the random excitation with a linear prediction synthesis filter. The implemented AMR-WB system used 218 kbytes of program memory and 92 kbytes of data memory. And its proper operation was confirmed by comparing a decoded speech signal sample-by-sample with that of PC-based simulation. Maximum required time of 5 75 ms for processing a frame of 20 ms of speech validates real-time operation of the Implemented system.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.283-286
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• 2002

This paper presents the straightness compensation system which is a device for improving the machining accuracy of ultra-precision machines by synchronizing the position of diamond tool tip with machine error motion. Sine it is actuated by piezoelectric actuator with highly nonlinear hysteresis characteristics, the feedback control schemes such as Proportional Integral(PI), are required and realized by measuring the displacements of diamond tool tip. for the better tracking performance, the controller was implemented using TMS320C32 32bit floating-point DSP which is fast so that the real-time control is possible. In addition, stand alone type DSP board was chosen fur the easy assembly into the ultra-precision machines. The experimental results show good command tracking performance and the motion error of the machine is satisfactorily compensated during the machining process.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.12a
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• pp.337-340
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• 2002

본 논문에서는 휠체어 시스템에 화자 독립 고립단어 인식을 위한 임베디드 시스템 설계에 관한 내용을 서술한다. 실제 환경에서는 잡음이 포함되어 있어 인식률을 저하시키므로, 잡음을 제거하는 방식 중 가장 간단한 방식인 스펙트럼 차감법(Spectral subtraction method)을 사용하여 잡음을 제거했다 전처리 단계에서는 12차 LPC&Cepstrum 방식을 사용했고, 인식 알고리즘은 DHMM (Discrete Hidden Markov Model)을 전반부 인식기로 사용했다. 이 알고리즘을 적용하기 위해서는 데이터 간소화를 위해 벡터양자화(Vector Quantization) 처리가 전제되어야한다 또한 인식알고리즘은 인식률을 향상을 위해 후처리 인식기로 신경망(MLP:Multi-layer Perceptron)을 통해서 인식률을 향상시켰다 화자 독립 시스템에 맞는 인식 단어의 구성은 총 7개단어로 남녀 총 25명 목소리로 구성하였다. 그리고 하드웨어 구성은 32-bits floating point 방식인 TMS320C32를 적용했고, 메모리 부분은 4Mbyte로 설계를 했으며, 메인보드의 설계는 현재 완성 단계에 있다.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.65-68
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• 1996

Robotic manipulators have become increasingly important in the field of flexible automation. High speed and high-precision trajectory tracking are indispensable capabilities for their versatile application. The need to meet demanding control requirement in increasingly complex dynamical control systems under significant uncertainties, leads toward design of intelligent manipulation robots. This paper presents a new approach to the design of neural control system using digital signal processors in order to improve the precision and robustness. The TMS32OC31 is used in implementing real time neural control to provide an enhanced motion control for robotic manipulators. In this control scheme, the networks introduced are neural nets with dynamic neurons, whose dynamics are distributed over all the, network nodes. The nets are trained by the distributed dynamic back propagation algorithm. The proposed neural network control scheme is simple in structure, fast in computation, and suitable for implementation of real-time, control. Performance of the neural controller is illustrated by simulation and experimental results for a SCARA robot.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.2
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• pp.201-206
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• 2004

This study attempted to develop a speech recognition module applied to a wheelchair for the physically handicapped. In the proposed speech recognition module, TMS320C32 was used as a main processor and Mel-Cepstrum 12 Order was applied to the pro-processor step to increase the recognition rate in a noisy environment. DTW (Dynamic Time Warping) was used and proven to be excellent output for the speaker-dependent recognition part. In order to utilize this algorithm more effectively, the reference data was compressed to 1/12 using vector quantization so as to decrease memory. In this paper, the necessary diverse technology (End-point detection, DMA processing, etc.) was managed so as to utilize the speech recognition system in real time

• Journal of Sensor Science and Technology
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• v.7 no.2
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• pp.124-130
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• 1998

High-speed 3D vision systems are essential for autonomous robot or vehicle control applications. In our study, a stereo vision process has been developed. It consists of three steps : extraction of edges in right and left images, matching corresponding edges and calculation of the 3D map. This process is implemented in a VME 150/40 Imaging Technology vision system. It is a modular system composed by a display, an acquisition, a four Mbytes image frame memory, and three computational cards. Programmable accelerator computational modules are running at 40 MHz and are based on TMS320C31 DSP with a $64{\times}32$ bit instruction cache and two $1024{\times}32$ bit internal RAMs. Each is equipped with 512 Kbytes static RAM, 4 Mbytes image memory, 1 Mbytes flash EEPROM and a serial port. Data transfers and communications between modules are provided by three 8 bit global video bus, and three local configurable pipeline 8 bit video bus. The VME bus is dedicated to system management. Tasks between DSPs are distributed as follows: two DSPs are used to edges detection, one for the right image and the other for the left one. The last processor computes the matching process and the 3D calculation. With $512{\times}512$ pixels images, this sensor generates dense 3D maps at a rate of about 1 Hz depending of the scene complexity. Results can surely be improved by using a special suited multiprocessors cards.

• Proceedings of the IEEK Conference
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• summer
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• pp.391-394
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5kbytes for program code. Maximum required time of 29.2ms for processing a frame of 32ms of speech validates real-time operation of the implemented system.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.145-148
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• 2000

본 논문은 범용 16bit Fixed-point DSP를 이용한 새로운 미국 DoD 2.4kbps MELP(Mixed Excitation Linear Predictive)보코더의 실시간 구현에 관한 것이다. 구현된 MELP보코더는 ROM 32.6kword, RAM 12.2kword를 가지며 40MIPS DSP에서 약 29MIPS를 필요로 하였다. 출력된 파형은 C simulator 와 Bit Exact한 출력 결과를 보여주었다. 실시간 구현된 MELP를 동일전송율의 2.4kbps AMBE와 음질 비교한 결과 AME보다는 MOS 0.2 음질 이 떨어졌다

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.74-84
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• 2000

This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.