• 제목/요약/키워드: TFT model

검색결과 78건 처리시간 0.022초

Dynamic Pixel Models for a-Si TFT-LCD and Their Implementation in SPICE

  • Wang, In-Soo;Lee, Gi-Chang;Kim, Tae-Hyun;Lee, Won-Jun;Shin, Jang-Kyoo
    • ETRI Journal
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    • 제34권4호
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    • pp.633-636
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    • 2012
  • A dynamic analysis of an amorphous silicon (a-Si) thin film transistor liquid crystal display (TFT-LCD) pixel is presented using new a-Si TFT and liquid crystal (LC) capacitance models for a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This dynamic analysis will be useful when predicting the performance of LCDs. The a-Si TFT model is developed to accurately estimate a-Si TFT characteristics of a bias-dependent gate to source and gate to drain capacitance. Moreover, the LC capacitance model is developed using a simplified diode circuit model. It is possible to accurately predict TFT-LCD characteristics such as flicker phenomena when implementing the proposed simulation model.

Effective Medium 모델 적용에 의한 poly-Si TFT 특성 Simulation (Poly-Si TFT characteristic simulation by applying effective medium model)

  • 박재우;김태형;노원열;최종선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2000년도 하계학술대회 논문집
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    • pp.320-323
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    • 2000
  • In the resent years, the Thin Film Transistor Liquid Crystal Display(TFT-LCD) have trend toward larger panel sizes and higher spatial and/or gray-scale resolution. In this trend, Because of its low field effect mobility, a-Si TFT is change to poly-Si TFT. In this paper, both effective-medium model of poly-Si TFTs and empirical capacitance model are applied to Pixel Design Array Simulation Tool (PDAST) and the pixel characteristics of TFT-LCD array were simulated, which were compared with the results calculated by Aim-Spice.

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데이터 배선 용량 최소화를 위한 비정질 실리콘 박막 트렌지스터 배열의 최적화 설계와 구현 (Optimal Design of a-Si TFT Array for Minimization of Data-line Capacitance and Its Implementation)

  • 김창원;윤정기;김선용;김종효
    • 대한의용생체공학회:의공학회지
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    • 제29권5호
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    • pp.392-399
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    • 2008
  • Thin-film transistor (TFT) arrays for an x-ray detector require quite different design concept from that of the conventional active-matrix liquid crystal devices (AM-LCDs). In this paper anew design of TFT array which uses only SiNx for passivation layer is described to meet the detector performance and the product availability simultaneously. For the purpose of optimizing the design parameters of the TFT array, a Spice simulation was performed. As a result, some parameters, such as the TFT width, the data line capacitance, and the storage capacitance, were able to be fixed. The other parameters were decided within a permissible range of the TFT process especially the photolithography process and the wet etch process. Then we adapted the TFT array which had been produced by the proposed design to our prototype model (FDXD-1417 and evaluated it clinically by comparing with a commercial model (EPEX, Hologic, Beford, USA). The results say that our prototype model is slightly better than EPEX system in chest PA images. So we can prove the technical usefulness and the commercial values of the proposed TFT design.

LTPO 소자의 머신 러닝 모델 개발 (Development of Machine Learning Model of LTPO Devices)

  • 은정수;안진수;이민석;곽우석;이종환
    • 반도체디스플레이기술학회지
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    • 제22권4호
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    • pp.179-184
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    • 2023
  • We propose the modeling methodology of CMOS inverter made of LTPO TFT using a machine learning. LTPO can achieve advantages of LTPS TFT with high electron mobility as a driving TFT and IGZO TFT with low off-current as a switching TFT. However, since the unified model of both LTPS and IGZO TFTs is still lacking, it is necessary to develop a SPICE-compatible compact model to simulate the LTPO current-voltage characteristics. In this work, a generic framework for combining the existing formula of I-V characteristics with artificial neural network is presented. The weight and bias values of ANN for LTPS and IGZO TFTs is obtained and implemented into PSPICE circuit simulator to predict CMOS inverter. This methodology enables efficient modeling for predicting LTPO TFT circuit characteristics.

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TFT-LCD 공정에서의 Color Filter 의 경제적 Lot Size 의 결정 (Determination of an Economic Lot Size of Color Filters in TFT-LCD Manufacturing)

  • 정봉주;손소영
    • 산업공학
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    • 제10권1호
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    • pp.47-55
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    • 1997
  • This paper deals with an assembly process of the TFT glasses and the color filters in LCD manufacturing. Two specific problems are presented and solved. One is a matching problem to find the best matches between a set of TFT glasses and a set of color filters, which result in the maximum number of good LCD assemblies. A simple mathematical model is constructed for this problem and an optimal solution can be obtained using an existing algorithm. The other is a main problem that requires a determination of an economic lot size of the color filters which are going to be assembled with a given set of TFT glasses. A Bayesian dynamic forecasting model is developed to predict the defective patterns of color filters. Based on the predicted defective rate of color filters, the minimum lot size of the color filters can be determined to minimize the probability of losing good TFT glasses and color filters.

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Precise Edge Detection Method Using Sigmoid Function in Blurry and Noisy Image for TFT-LCD 2D Critical Dimension Measurement

  • Lee, Seung Woo;Lee, Sin Yong;Pahk, Heui Jae
    • Current Optics and Photonics
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    • 제2권1호
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    • pp.69-78
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    • 2018
  • This paper presents a precise edge detection algorithm for the critical dimension (CD) measurement of a Thin-Film Transistor Liquid-Crystal Display (TFT-LCD) pattern. The sigmoid surface function is proposed to model the blurred step edge. This model can simultaneously find the position and geometry of the edge precisely. The nonlinear least squares fitting method (Levenberg-Marquardt method) is used to model the image intensity distribution into the proposed sigmoid blurred edge model. The suggested algorithm is verified by comparing the CD measurement repeatability from high-magnified blurry and noisy TFT-LCD images with those from the previous Laplacian of Gaussian (LoG) based sub-pixel edge detection algorithm and error function fitting method. The proposed fitting-based edge detection algorithm produces more precise results than the previous method. The suggested algorithm can be applied to in-line precision CD measurement for high-resolution display devices.

유효면적과 평균속도를 고려한 TFT의 해석적 Drain 전류 모델 (Analytical Model of TFT Drain Current based on Effective Area and Average Velocity)

  • 정태희;원창섭;류세환;한득영;안형근
    • 한국전기전자재료학회논문지
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    • 제21권3호
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    • pp.197-202
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    • 2008
  • In this paper, we proposed an analytical model for TFT which has series of the polycrystalline structures. An average speed is defined as carrier speed by the electric field. The effective square is suggested as the area of grain without depletion for the changed grain size. First, physical parameters such as grain size, channel lenght and trap density, have been changed to prove the validity of the average speed model and the value of the effective square has been estimated through drain-source current.

TFT-LCD 특성 분석을 위한 poly-Si TFT 소자 모델링 및 회로 시뮬레이션 (Modeling of Poly-Si TFT and Circuit Simulation for the Analysis of TFT-LCD Characteristics)

  • 손명식;류재일;심성융;장진;유건호
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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    • pp.314-317
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    • 2000
  • In order to analyze the characteristics of complicated TFT-LCD (Thin Film Transistor-Liquid Crystal Display) circuits, it is indispensible to use simulation programs. In this study, we present a systematic method of extracting the input parameters of poly-Si TFT for Spice simulation. This method is applied to two different types of poly-Si TFTs fabricated in our group with good results. Among the Spice simulators, Pspice has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT model on the Pspice simulator, which would contribute to efficient simulations of poly-Si TFT-LCD pixels and arrays.

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다결정 실리콘 TFT의 누설전류 모델링에 관한 연구 (A Study on the Modeling of Leakage Current in Polysilicon TFT)

  • 박정훈;이주창;김영식;이동희;성만영
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1993년도 하계학술대회 논문집 B
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    • pp.1250-1252
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    • 1993
  • Enhancement mode n-channel TFT leakage current(off current : $V_G<0$) that is little agreement on the conduction mechanism is major disadvantage of poly-silicon TFT in practical use, characteristic analysis and model ing. In this paper, new modeling of leakage current is proposed. The activation energy of leakage current, which is dependent on gate voltage, and leakage current dependent on poly silicon thickness are plausibly explained with this model. This model indicate that the reduction of leakage current is attributable to a decrease of maximum laterial electric field strength in the drain depletion region and to the density of trap.

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비정질 실리코 박막 트랜지스터 히스테리시스 특성의 수학적인 모델 (Mathematical Modeling of Hysteresis Characteristics of a-Si:H TFT)

  • Lee, Woo-Sun;Kim, Byung-In
    • 대한전기학회논문지
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    • 제43권7호
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    • pp.1135-1143
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    • 1994
  • We fabricate a bottom gate a-Si:H TFT on N-Type <100> Si wafer. According to the Variation of gate and drain voltage, the hysteresis characteristic curves were measured experimentally. Also, we proposed model equation and showed that the model predict the hysteresis characteristic successfully. Drain current on the hysteresis characteristic curve showed an exponential variation. Hysteresis area of TFT increased with the drain voltage increase and decreases with the drain voltage decrease.

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