• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.313-325
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• 1996

This paper presents a new architecture for full-search block-matching motion estimation. The architecture is based on linear systolic arrays. High speed operation is obtained by feeding reference data, search data, and control signals into the linear systolic array in a pipelined fashion. Input data are fed into the linear systolic array at a half of the processor speed, reducing the required data bandwidth to half. The proposed architecture has a good scalability with respect to the number of processors and input bandwidth when the size of reference block and search range change.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.347-350
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• 2002

In the input buffer switch system, VOQ(Virtual Output Queue) archives 100% throughput. The VOQ with the systolic architecture maintains an uniform performance regardless of a number of Packet class and output port, so that it doesn't have a limitation of scalability. In spite of these advantages, the systolic architecture VOQ is difficult to change sorting order In this paper, we Proposed a systolic architecture VOQ which support weighted round robin(WRR) algorithm to provide with flow control service.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.481-493
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• 2011

Multiple-input multiple-output (MIMO) technology provides high data rate and enhanced quality of service for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity suboptimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-maximum-likelihood performance. In this paper, we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "Lenstra-Lenstra-Lov$\acute{a}$sz (LLL) lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction-LLL is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lov$\acute{a}$sz condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LR-aided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average field-programmable gate array processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

• Journal of Korea Society of Industrial Information Systems
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• v.5 no.3
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• pp.117-124
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• 2000

A systolic array is a parallel processing system which consists of processing elements of basic computation capabilities, connected with regular and local communication lines. It has been known that a systolic array is on of effective systems to solve complicated communication problems occurred between densely connected neurons on ANN(Artificial Neural Network). In this paper, a systolic array simulator for the back-propagation ANN, which automatically constructs the proper systolic array for a given number of neurons of the ANN, is designed and constructed. With animation techniques of the simulators, it is easy for users to be able to examine the execution of the back-propagation algorithm on the designed systolic array step by step. Moreover the simulator can perform forward and backward operations of the back-propagation algorithm either in sequence or in parallel on the designed systolic array. Parallel execution can be performed by feeding continuous input patterns and by executing bidirectional propagations on all of processing elements of a systolic array at the same time.

• The Journal of Information Technology
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• v.10 no.3
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• pp.33-45
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• 2007

Systolic Array Processor is used for designing the special purpose processor in Digital Signal Processing, Computer Graphics, Neural Network Applications etc., since it has the characteristic of parallelism, pipeline processing and architecture of regularity. But, in case of using general design method, it has intial waiting period as large as No. of PE-1. And if the connected system needs parallel and simultaneous outputs, processor has some problems of the performance, since it generates only one output at each clock in output state. So in this paper, one dimensional Systolic Array Processor that is designed according to the dependance of data and operations using the partitioned sub-matrix is proposed for the purpose of improving the performance. 1-D Systolic Array using 4 partitioned sub-matrix has efficient method in case of considering those two problems.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1995.11a
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• pp.163-172
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• 1995

In this paper, the bit-level 1-dimensionl systolic array for modular multiplication are designed. First of all, the parallel algorithms and data dependence graphs from Walter's Iwamura's methods based on Montgomery Algorithm for modular multiplication are derived and compared. Since Walter's method has the smaller computational index points in data dependence graph than Iwamura's, it is selected as the base algorithm. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays ale obtained and then are evaluated by various criteria. Modifying the array derived from 〔0,1〕 projection direction by adding a control logic and serializing the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for modular expandable and is good for fault tolerance due to unidirectional paths. And so, it is suitable for RSA Cryptosystem which deals with the large size and many consecutive message blocks.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.9
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• pp.62-69
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• 1996

In this paper, the bit-level 1-dimensional systolic array for modular multiplication is designed. First of all, the parallel algorithm and data dependence graph from walter's method based on montgomery algorithm suitable for array design for modular multiplication is derived. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays are obtained and then are evaluated by various criteria. As it is modified the array which is derived form [0,1] projection direction by adding a control logic and it is serialized the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for expansile module and it is easy for fault tolerance due to unidirectional paths. It is suitable for RSA cryptosystem which deals iwth the large size and many consecutive message blocks.

• The Transactions of the Korea Information Processing Society
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• v.4 no.5
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• pp.1380-1390
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• 1997

This paper presents a systolic array design method which derives 1 or 2 dimensional optimal planar systolic arrays from a given n dimensional problem represented as a regular recurrence equation and its implementation called a systolic array design system(SADS).The SADS parses a regular recurrence equation and gets the information such as problem space, data dependence vectors. and intial data positions. Systolic arrays are automati-cally derived by the space-time transformation form the information to be abeaired in the parsing phase.The SADS allows us to verify the parallel execution of the derived systolic aooay through the graghical interface.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.6
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• pp.556-565
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• 1991

Using the WDZ decomposition algorithm, a parallel algorithm is presented for solving the linear system Ax=b which has an nxn nonsingular tridiagonal matrix. For implementing this algorithm a CAM systolic arrary is proposed, and each processing element of this array has its own CAM to store the nonzero elements of the tridiagonal matrix. In order to evaluate this array the algorithm presented is compared to theis compared to the LU decomposition algorithm. It is found that the execution time of the algorithm presented is reduced to about 1/4 than that of the LU decomposition algorithm. If each computation process step can be dome in one time unit, the system of eqations is solved in a systolic fashion without central control is obtained in 2n+1 time steps.

• Journal of Chest Surgery
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• v.29 no.8
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• pp.867-874
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• 1996

This study was designed to assess the left ventricular peak systolic pressure/end-systolic volume (PSP/ESV) ratio in predicting symptomatic improvement with valve replacement in patients with aortic regurgitation and enlarged left von'lrlcular volume. We studied 21 patients (15 men and 6 women aged 15 to 60 years) with moderate or severe aortic regur- gitation, no other cardiovascular abnormalities and left ventricular end-systolic volume over 60 m11m2. In this group we assessed the preoperative variables which routinely were measured at cardiac catheterlzation to predict symptomatic improvement with valve replacement. Six months after operation, symptoms were alleviated in 13 patients(62%), and unchanged in 8()8%). By multivariate analysis, the PSP/ESV rati was a strong predictor for functional class 6 months after surgery(p=0.005) and also for change- in functional class prior to an operation to 6 months postoperatively(p=0.0)2). By 6 months after receiving valve replacement, all patients with a ratio over 1. 71 mmHglml/m'were in functional class I or II , in contrast, of those with a ratio < 1.71 mmHg/ml/m2, 40% were in functional class III. The PSP/ESV ratio may help to predict which patients with aortic regurgitation and enlarged left ven- tricular end-systolic volume will have symptomatic improvement with valve replacement.