• Title/Summary/Keyword: System-on-a-Chip (SoC)

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Design and Implementation of ARM based Network SoC Processor (ARM 기반의 네트워크용 SoC(System-on-a-chip) 프로세서의 설계 및 구현)

  • 박경철;박영원
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.53 no.6
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    • pp.440-445
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    • 2004
  • The design and implementation of a Network Processor using System-on-a-chip(SoC) technology is presented. The proposed network processor can handle several protocols as well as various types of traffics simultaneously. The proposed SoC consists of ARM processor core, ATM block, AAL processing block, Ethernet block and a scheduler. The scheduler guarantees QoS of the voice traffic and supports multiple AAL2 packet. The SoC is manufactured on the 0.35 micron fabrication line of HYNIX semiconductor, the total number of gates is about 312,000, for a maximum operating frequency of over to 50㎒.

A Real-Time Operating System for System-on-Chip Design and Verification (SoC(System-on-Chip) 설계와 검증을 지원하는 실시간운영체제)

  • Kim, Ji-Min;Ryu, Min-Soo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2005.05a
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    • pp.1679-1682
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    • 2005
  • 최근 SoC를 포함하는 대부분의 임베디드시스템에서는 RTOS가 선택이 아닌 필수적인 구성요소가 됨에 따라 SoC 개발의 초기단계에서부터 RTOS를 도입하는 것이 바람직하다. 하지만, 기존의 범용 RTOS가 제공하는 기능은 대부분 응용 소프트웨어의 개발과 수행을 위한 것으로 SoC 개발 및 검증에는 적합하지 않은 문제점을 가지고 있다. 본 연구에서는 SoC 개발을 위해 운영체제가 만족시켜야할 요구사항을 제시하고, 소프트웨어의 재사용성과 SoC의 검증을 함께 지원하는 VPOS(Verification-Purpose OS)를 개발하였다. VPOS는 초경량의 단순한 계층적 구조(layered structure)를 가지는 RTOS로서 소프트웨어 재사용을 위해 POSIX 표준 API, 유닉스 호환 디바이스 드라이버 인터페이스, HAL 등을 제공한다. 또한 SoC 설계의 검증을 위해 RT 수준의 통합시뮬레이션에 적합한 커널 구조 및 최적화된 코드, 하드웨어 테스트를 위한 쉘 명령어, 응용 소프트웨어의 디버깅을 위한 KREM(kernel resource and event monitoring) 등의 특징을 함께 제공한다.

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The implementation of DC motor controller based on SOC

  • Lee, Sung-Ui;Seo, Jae-Kwan;Oh, Sung-Nam;Park, Kyi-Kae;Kim, Kab-Il
    • Proceedings of the KIEE Conference
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    • 2002.11c
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    • pp.365-369
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    • 2002
  • In this paper, DC motor controller has been designed by using SoC. SoC is short for System on a chip. This is a methodology that both a processor and some applications are integrated in a chip. In order to design this system based on SoC, PIC 16C57 has been selected as a processor because it has not too many instruction sets and simple data path named a harvard structure. And motor control module has been programmed by using VHDL. The advantages of the design based on SoC are as follows: simple structure, high speed working, easily verifying and simulating the system.

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System-on-chip single event effect hardening design and validation using proton irradiation

  • Weitao Yang;Yang Li;Gang Guo;Chaohui He;Longsheng Wu
    • Nuclear Engineering and Technology
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    • v.55 no.3
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    • pp.1015-1020
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    • 2023
  • A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system watchdog. Irradiation tests utilized 70 and 90 MeV proton beams to examine its performance through comparative analysis. Via examining SEEs in on-chip memory (OCM), compared with the trial without applying the multi-layer design, the test results demonstrate that the adopted multi-layer design can effectively mitigate SEEs in the SoC.

Optimal Design of Network-on-Chip Communication Sturcture (Network-on-Chip에서의 최적 통신구조 설계)

  • Yoon, Joo-Hyeong;Hwang, Young-Si;Chung, Ki-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.8
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    • pp.80-88
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    • 2007
  • High adaptability and scalability are two critical issues in implementing a very complex system in a single chip. To obtain high adaptability and scalability, novel system design methodology known as communication-based system design has gained large attention from SoC designers. NoC (Network-on-Chip) is such an on-chip communication-based design approach for the next generation SoC design. To provide high adaptability and scalability, NoCs employ network interfaces and routers as their main communication structures and transmit and receive packetized data over such structures. However, data packetization, and routing overhead in terms of run time and area may cost too much compared with conventional SoC communication structure. Therefore, in this research, we propose a novel methodology which automatically generates a hybrid communication structure. In this work, we map traditional pin-to-pin wiring structure for frequent and timing critical communication, and map flexible and scalable structure for infrequent, or highly variable communication patterns. Even though, we simplify the communication structure significantly through our algorithm the connectivity or the scalability of the communication modules are almost maintained as the original NoC design. Using this method, we could improve the timing performance by 49.19%, and the area taken by the communication structure has been reduced by 24.03%.

SNP: A New On-Chip Communication Protocol for SoC (SNP : 시스템 온 칩을 위한 새로운 통신 프로토콜)

  • Lee Jaesung;Lee Hyuk-Jae;Lee Chanho
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.9
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    • pp.465-474
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    • 2005
  • For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

ARM Professor-based programmable BIST for Embedded Memory in SoC (SoC 내장 메모리를 위한 ARM 프로세서 기반의 프로그래머블 BIST)

  • Lee, Min-Ho;Hong, Won-Gi;Song, Jwa-Hee;Chang, Hoon
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.6
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    • pp.284-292
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    • 2008
  • The density of Memory has been increased by great challenge for memory technology; therefore, elements of memory become more smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. In addition, as the number of storage elements per chip increases, the test cost becomes more remarkable as the cost per transistor drops. Recent development in system-on-chip(SoC) technology makes it possible to incorporate large embedded memories into a chip. However, it also complicates the test process, since usually the embedded memories cannot be controlled from the external environment. We present a ARM processor-programmable built-in self-test(BIST) scheme suitable for embedded memory testing in the SoC environment. The proposed BIST circuit can be programmed vis an on-chip microprocessor.

VHDL Design of Hybrid Filter Bank for MPEG Audio Decoder and Verification using C-to-VHDL Interface (MPEG 오디오 복호기용 하이브리드 필터의 VHDL 설계 및 C 언어 인터페이스에 의한 기능 검증)

  • 국일호;박종진;박원태;조원경
    • Journal of the Institute of Electronics Engineers of Korea TE
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    • v.37 no.5
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    • pp.56-61
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    • 2000
  • Silicon semiconductor technology agrees that the number of transistors on a chip will keep growing exponentially, and it is pushing technology toward the System-On-Chip. In SoC Design, Specification at system level is key of success. Executable Specification reduces verification time. This Paper describes the design of IMDCT for MPEG Audio Decoder employing system-level design methodology and Executable Specification Methodology in the VHDL simulator with FLI environment.

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The Research of System-On-Chip Design for Railway Signal System (철도신호를 위한 단일칩 개발에 관한 연구)

  • Park, Joo-Yul;Kim, Hyo-Sang;Lee, Joon-Hwan;Kim, Bong-Taek;Chung, Ki-Seok
    • Proceedings of the KSR Conference
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    • 2008.06a
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    • pp.572-578
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    • 2008
  • As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.

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EC-DSA Implementation using Security SoC with built-in ECC Core (ECC 코어가 내장된 보안 SoC를 이용한 EC-DSA 구현)

  • Yang, Hyeon-Jun;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2021.05a
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    • pp.63-65
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    • 2021
  • This paper describes an integrated H/W-S/W implementation of elliptic curve digital signature algorithm (EC-DSA) using a security system-on-chip (SoC). The security SoC uses the Cortex-A53 APU as CPU, and the hardware IPs of high-performance elliptic curve cryptography (HP-ECC) core and SHA3 (secure hash algorithm 3) hash function core are interfaced via AXI4-Lite bus protocol. The signature generation and verification processes of EC-DSA were verified by the implementation of the security SoC on a Zynq UltraScale+ MPSoC device.

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