• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.2
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• pp.128-137
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• 1999

Recently the pelionnance of CO2 arc welding machine has been advanced significantly through the adoption of i invelter circuit topology. which made it possible to improve welding perfonnances such as spatter generation and bead s state. But the conventional inverter arc welding machine generates constant output voltage which cause much spatter g generation dUling short-circuit and arc start time because it is unable to control output current instantaneously. So this p paper representes wavefCnm controlled inverter arc welding machine which control the wavefonn of welding current and t thus to suppress the spatter generation. And the system designed in this paper is the digital controller using single chip m microprocessor of 80C196KC. As a result of perfonnance test for this system, the spatter generation is reduced and s shOlt-circuit time period is stabilized compared to conventional one. And more by using switched mode rectifier for A AC/DC power convelter. unity power factor is maintained and low order halmonic spectrum is supressed.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.699-708
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• 2006

Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.32-40
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• 2016

IEEE 802.15.4 is the one of the protocols for radio communication in a personal area network. Because of low cost and low power communication for IoT communication, it requires the highest optimization level in the implementation. Recently, the studies of location aware algorithm based on IEEE802.15.4 standard has been achieved. Location estimation is performed basically in equal consideration of reference node information and blind node information. However, an error is not calculated in this algorithm despite the fact that the coordinates of the estimated location of the blind node include an error. In this paper, we enhanced a conventual maximum likelihood estimation using weighted coefficient and implement the hardwired location aware engine for small code size and low power consumption. On the field test using test-beds, the suggested hardware based location awareness method results better accuracy by 10 percents and reduces both calculation and memory access by 30 percents, which improves the systems power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.73-82
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• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of Korean Society of Forest Science
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• v.110 no.2
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• pp.217-232
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• 2021

This study calculated the productivity and cost of extraction and processing of logging residues by cut-to-length (CTL) and whole-tree (WT) harvesting methods. In addition, the comparative analysis of the characteristics of wood chip fuel to examine whether it was suitable for the fuel conditions of the energy facility. In the harvesting and processing system to produce the wood chips of logging residues the system productivity and cost of the CTL harvesting system were 1.6 Gwt/SMH and 89,865 won/Gwt, respectively. The productivity and cost of the WT harvesting system were 2.9 Gwt/SMH and 72,974 won/Gwt, respectively. The WT harvesting productivity increased 1.3times while harvesting cost decreased by 18.7% compared to the CTL harvesting system. The logging residues of wood chips were not suitable for CTL wood chips based on International Organization for Standardization (ISO 17225-4:2021) and South Korea standard (NIFoS, 2020), but the quality (A2, Second class) was improved through screening operation. The WT-unscreened wood chips conformed to NIFoS standard (second class) and did not conform to ISO but were improved through screening operation (Second class). In addition to the energy facility in plant A, all wood chips except CTL-unscreened wood chips were available through drying processing. The WT-unscreened wood chips were the lowest at 99,408 won/Gwt. Plants B, C, and D had higher moisture content than plant A, so WT-unscreened wood chips without drying processing were the lowest at 57,204 won/Gwt. Therefore, the production of logging residues should improve with operation methods that improve the quality of wood chips required for applying the variable biomass and energy facility.