• Title/Summary/Keyword: System throughput

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A Scalable OWL Horst Lite Ontology Reasoning Approach based on Distributed Cluster Memories (분산 클러스터 메모리 기반 대용량 OWL Horst Lite 온톨로지 추론 기법)

  • Kim, Je-Min;Park, Young-Tack
    • Journal of KIISE
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    • v.42 no.3
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    • pp.307-319
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    • 2015
  • Current ontology studies use the Hadoop distributed storage framework to perform map-reduce algorithm-based reasoning for scalable ontologies. In this paper, however, we propose a novel approach for scalable Web Ontology Language (OWL) Horst Lite ontology reasoning, based on distributed cluster memories. Rule-based reasoning, which is frequently used for scalable ontologies, iteratively executes triple-format ontology rules, until the inferred data no longer exists. Therefore, when the scalable ontology reasoning is performed on computer hard drives, the ontology reasoner suffers from performance limitations. In order to overcome this drawback, we propose an approach that loads the ontologies into distributed cluster memories, using Spark (a memory-based distributed computing framework), which executes the ontology reasoning. In order to implement an appropriate OWL Horst Lite ontology reasoning system on Spark, our method divides the scalable ontologies into blocks, loads each block into the cluster nodes, and subsequently handles the data in the distributed memories. We used the Lehigh University Benchmark, which is used to evaluate ontology inference and search speed, to experimentally evaluate the methods suggested in this paper, which we applied to LUBM8000 (1.1 billion triples, 155 gigabytes). When compared with WebPIE, a representative mapreduce algorithm-based scalable ontology reasoner, the proposed approach showed a throughput improvement of 320% (62k/s) over WebPIE (19k/s).

A Screening Method for Src Homology 3 Domain Binding Blockers Based on Ras Signaling Pathway

  • Ko, Woo-Suk;Yoon, Sun-Young;Kim, Jae-Won;Lee, Choong-Eun;Han, Mi-Young
    • BMB Reports
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    • v.30 no.5
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    • pp.303-307
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    • 1997
  • Grb2, which is composed of a Src homology 2 (SH2) domain and two Src homology 3 (SH3) domains, is known to serve as an adaptor protein in signaling for Ras activation. Thus, a blocker of the Grb2 interactions with other proteins can be a potential candidate for an anticancer drug. In this study, we have developed a high throughput screening method for SH3 domain binding ligands and blockers. Firstly, we made and purified the glutathione S-transferase (GST)-fusion proteins with the Grb2 SH2 and SH3 domains, and the entire Grb2. This method measures the binding of a biotin-labeled oligopeptide, derived from a Grb2/SH3 binding motif in the hSos, to the GST-fusion proteins, which are precoated as glutathione S-transferase fusion protein on a solid phase. When $1\;{\mu}g$ of each fusion protein was used to coat the wells, both N- and C- terminal SH3 the domains as well as the whole of Grb2 were able to interact with the biotin-conjugated ligand peptide, while the SH2 domain and GST alone showed no binding affinity. Although N- and C- terminal SH3 domains showed an increase of binding to the ligand peptide in proportion to the amount of peptide, the GST fusion protein with Grb2 demonstrated much higher binding affinity. GST-Grb2 coating on the solid phase showed a saturation curve; 66 and 84% of the maximal binding was observed at 100 and 300 ng/$100\;{\mu}l$, respectively. This binding assay system was peptide sequence-specific, showing a dose-dependent inhibition with the unlabeled peptide of SH3 binding motif. Several other peptides, such as SH2 domain binding motifs and PTB domain binding motif, were ineffective to inhibit the binding to the biotin-conjugated ligand peptide. These results suggest that our method may be useful to screen for new anticancer drug candidates which can block the signaling pathways mediated by SH3 domain binding.

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An Efficient TCP Buffer Tuning Algorithm based on Packet Loss Ratio(TBT-PLR) (패킷 손실률에 기반한 효율적인 TCP Buffer Tuning 알고리즘)

  • Yoo Gi-Chul;Kim Dong-kyun
    • The KIPS Transactions:PartC
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    • v.12C no.1 s.97
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    • pp.121-128
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    • 2005
  • Tho existing TCP(Transmission Control Protocol) is known to be unsuitable for a network with the characteristics of high RDP(Bandwidth-Delay Product) because of the fixed small or large buffer size at the TCP sender and receiver. Thus, some trial cases of adjusting the buffer sizes automatically with respect to network condition have been proposed to improve the end-to-end TCP throughput. ATBT(Automatic TCP fluffer Tuning) attempts to assure the buffer size of TCP sender according to its current congestion window size but the ATBT assumes that the buffer size of TCP receiver is maximum value that operating system defines. In DRS(Dynamic Right Sizing), by estimating the TCP arrival data of two times the amount TCP data received previously, the TCP receiver simply reserves the buffer size for the next arrival, accordingly. However, we do not need to reserve exactly two times of buffer size because of the possibility of TCP segment loss. We propose an efficient TCP buffer tuning technique(called TBT-PLR: TCP buffer tuning algorithm based on packet loss ratio) since we adopt the ATBT mechanism and the TBT-PLR mechanism for the TCP sender and the TCP receiver, respectively. For the purpose of testing the actual TCP performance, we implemented our TBT-PLR by modifying the linux kernel version 2.4.18 and evaluated the TCP performance by comparing TBT-PLR with the TCP schemes of the fixed buffer size. As a result, more balanced usage among TCP connections was obtained.

CARA: Collision-Aware Rate Adaptation for IEEE 802.11 WLANs (CARA: IEEE 802.11 무선랜에서 충돌을 인지한 적응적 전송속도 조절기법)

  • Kim, Jong-Seok;Kim, Seong-Kwan;Choi, Sung-Hyun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.2A
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    • pp.154-167
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    • 2006
  • Today's IEEE 802.11 WLANs(Wireless LANs) provide multiple transmission rates so that different rates can be exploited in an adaptive manner depending on the underlying channel condition in order to maximize the system performance. Many rate adaptation schemes have been proposed so far while most(if not all) of the commercial devices implement a simple open-loop rate adaptation scheme(i.e., without feedback from the receiver), called ARF(Automatic Rate Fallback) due to its simplicity. A key problem with such open-loop rate adaptation schemes is that they do not consider the collision effect, and hence, malfunction severely when many transmission failures are due to collisions. In this paper, we propose a novel rate-adaptation scheme, called CARA(Collision-Aware Rate Adaptation). The key idea of CARA is that the transmitter station combines adaptively the Request-to-Send/Clear-to-Send(RTS/CTS) exchange with the Clear Channel Assessment(CCA) functionality to differentiate frame collisions from frame transmission failures cause by channel errors. Therefore, compared with other open-loop rate adaptation schemes, CATA is more likely to make the correct rate adaptation decisions. Through extensive simulation runs, we evaluate our proposed scheme to show that our scheme yields significantly higher throughput performance than the existing schemes in both static and time-varying fading channel environments.

Adaptive Collision Resolution Algorithm for Improving Delay of Services in B-WLL System (B-WLL 시스템에서 서비스 지연 향상을 위한 충돌 해소 알고리즘)

  • Ahn, Kye-Hyun;Park, Byoung-Joo;Baek, Seung-Kwon;Kim, Eung-Bae;Kim, Young-Chon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.1B
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    • pp.42-48
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    • 2002
  • In broadband wireless networks, the effective meeting of the QoS guarantees may strongly depend on the Contention Resolution Algorithm used in the uplink contention period. The time it takes a station to transmit a successful request to the base station, or request delay, must be kept low even during periods of high contention. If a request suffers many collisions, it cannot rely on the preemptive scheduler to receive low access delays. However, the conventional collision resolution algorithm has a problem that all collided stations are treated equally regardless of their delay from previous contention periods. Some requests may have very long request delay caused by continuous collisions. In this paper, we propose an adaptive collision resolution algorithm for fast random access in broadband wireless networks. The design goal is to provide quick access to the request with a high number of collisions. To do this, the proposed algorithm separates the whole contention region into multiple sub regions and permits access through each sub region only to the requests with equal number of collisions. The sub region is adaptively created according to the feedback information of previous random access. By simulation, the proposed algorithm can improve the performance in terms of throughput, random delay and complementary distribution of random delay by its ability to isolate higher priorities from lower ones. We can notice the algorithm provides efficiency and random access delay in random access environment.

Design and Implementation of 8b/10b Encoder/Decoder for Serial ATA (직렬 ATA용 8b/10b 인코더와 디코더 설계 및 구현)

  • Heo Jung-Hwa;Park Nho-Kyung;Park Sang-Bong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.1A
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    • pp.93-98
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    • 2004
  • Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

Design and Implementation of ISO/IEEE 11073 DIM Transmission Structure Based on oneM2M for IoT Healthcare Service (사물인터넷 헬스케어 서비스를 위한 oneM2M기반 ISO/IEEE 11073 DIM 전송 구조 설계 및 구현)

  • Kim, Hyun Su;Chun, Seung Man;Chung, Yun Seok;Park, Jong Tae
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.4
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    • pp.3-11
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    • 2016
  • In the environment of Internet of Things (IoT), IoT devices are limited by physical components such as power supply and memory, and also limited to their network performance in bandwidth, wireless channel, throughput, payload, etc. Despite these limitations, resources of IoT devices are shared with other IoT devices. Especially, remote management of the information of devices and patients are very important for the IoT healthcare service, moreover, providing the interoperability between the healthcare device and healthcare platform is essential. To meet these requirements, format of the message and the expressions for the data information and data transmission need to comply with suitable international standards for the IoT environment. However, the ISO/IEEE 11073 PHD (Personal Healthcare Device) standards, the existing international standards for the transmission of health informatics, does not consider the IoT environment, and therefore it is difficult to be applied for the IoT healthcare service. For this matter, we have designed and implemented the IoT healthcare system by applying the oneM2M, standards for the Internet of Things, and ISO/IEEE 11073 DIM (Domain Information Model), standards for the transmission of health informatics. For the implementation, the OM2M platform, which is based on the oneM2M standards, has been used. To evaluate the efficiency of transfer syntaxes between the healthcare device and OM2M platform, we have implemented comparative performance evaluation between HTTP and CoAP, and also between XML and JSON by comparing the packet size and number of packets in one transaction.

40Gb/s Foward Error Correction Architecture for Optical Communication System (광통신 시스템을 위한 40Gb/s Forward Error Correction 구조 설계)

  • Lee, Seung-Beom;Lee, Han-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.101-111
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    • 2008
  • This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

A LDPC Decoder for DVB-S2 Standard Supporting Multiple Code Rates (DVB-S2 기반에서 다양한 부호화 율을 지원하는 LCPC 복호기)

  • Ryu, Hye-Jin;Lee, Jong-Yeol
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.118-124
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    • 2008
  • For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

Planning for Intra-Block Remarshaling to Enhance the Efficiency of Loading Operations in an Automated Container Terminal (자동화 컨테이너 터미널의 적하 작업 효율 향상을 위한 블록 내 재정돈 계획 수립 방안)

  • Park, Ki-Yeok;Park, Tae-Jin;Kim, Min-Jung;Ryu, Kwang-Ryel
    • Journal of Intelligence and Information Systems
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    • v.14 no.4
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    • pp.31-46
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    • 2008
  • A stacking yard of a container terminal is a space for temporarily storing the containers that are carried in or imported until they are carried out or exported. If the containers are stacked in an inappropriate way, the efficiency of operation at the time of loading decreases significantly due to the rehandlings. The remarshaling is the task of rearranging containers during the idle time of transfer crane for the effective loading operations. This paper proposes a method of planning for remarshaling in a yard block of an automated container terminal. Our method conducts a search in two stages. In the first stage, the target stacking configuration is determined in such a way that the throughput of loading is maximized. In the second stage, the crane schedule is determined so that the remarshaling task can be completed as fast as possible in moving the containers from the source configuration to the target configuration. Simulation experiments have been conducted to compare the efficiency of loading operations before and after remarshaling. The results show that our remarshaling plan is really effective in increasing the efficiency of loading operation.

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