• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.120-123
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• 2000

In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.333-341
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• 2015

In this paper, a 0.5~4 GHz frequency synthesizer having good phase noise performance is proposed. Wideband output frequencies of the synthesizer were synthesized using DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology in order to obtain fast settling time. Also in order to get good phase noise performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked by the 100 MHz reference oscillator using SPD(Sample Phase Detector). The phase noise performance of wideband frequency synthesizer was estimated and the results were compared with the measured ones. The measured phase noise of the frequency synthesizer was less then -121 dBc @ 100 kHz at 4 GHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1099-1106
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• 2018

In this paper, we developed and then analyzed the specifications of the frequency synthesizer which was applied to long range MFR (Multi-function Radar). These specifications were able to guarantee the functions and performance of MFR. MFR was the radar system that used phase array for electronically scanning. This frequency synthesizer made various frequency signals including to STALO (Stable Local Oscillator) for MFR. By analyzing the MFR requirements, we choose the optimal frequency synthesis method and then we got the best performance and functionality including to physical size for this system. We designed and fabricated DDS (Direct Digital Synthesizer)-driven Offset-PLL (Phase Locked Loop) synthesizer to meet the requirements which were low phase noise, fast switching time and low spurious. This synthesizer had less than -131dBc/Hz@100kHz phase noise and less than $4.1{\mu}s$ switching time, respectively.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.181-184
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• 2008

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.165-168
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• 2008

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.76-84
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• 1999

For FH/SS communication, We discussed the method of indirect frequency synthesizer in several methods. The problem of sing1e frequency synthesizer using with PLL is a varied coefficient value of damping factor in frequency hopping time, which is caused unstable frequency. So. for stable frequency synthesizer, a coefficient of damping factor must be optimized and synthesized to be removed excessive response time. In this paper, we studied FH using with double loop frequency synthesizer which takes stable frequency. We made up a simulator and had a good performance(real time speed).

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.137-140
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• 2005

A frequency synthesizer of 10 GHz $\sim$ 11 GHz for FMCW radar is designed and implemented by the form of indirect frequency synthesizer of a single loop structure. The synthesizer uses a high speed digital PLL chip. It is difficult to divide directly by using a program counter of PLL chip because the output frequency of VCO is 10 GHz $\sim$ 11 GHz, so we lower the frequency to 625 MHz $\sim$ 687.5 MHz by using a prescaler, and then divide the frequency by the program counter. The output frequency sweep of VCO from 10 GHz to 11 GHz is measured.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.5
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• pp.818-824
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• 2011

In this paper, we proposed a phase noise model of a frequency synthesizer for a radar system. Especially, it was proposed a phase noise model in a DAS(Direct Analog Synthesizer) and a frequency up converter system using Leeson's model. The proposed phase noise model was derived from the measurement data of model 1 and evaluated by adapting to model 2 and model 3 frequency synthesizers. The prediction phase noise by modeling was totally matched to the measured data and the effective analysis of the phase noise was done in a frequency synthesizer and a frequency converter of radar system.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.11a
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• pp.208-209
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• 2005

A frequency synthesizer of 10 GHz ${\sim}$ 11 GHz for FMCW radar is designed and implemented by the form of indirect frequency synthesizer of a single loop structure. The synthesizer uses a high speed digital PLL chip. It is difficult to divide directly by using a program counter of PLL chip because the output frequency of VCO is 10 GHz ${\sim}$ 11 GHz, so we lower the frequency to 625 MHz ${\sim}$ 687.5 MHz by using a prescaler, and then divide the frequency by the program counter. The output frequency sweep of VCO from 10 GHz to 11 GHz is measured.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.3
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• pp.444-448
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• 2006

In this paper, a frequency synthesizer for X-band FMCW radars is proposed. Some X-band FMCW radars have been used as a level sensor for tanker ship and the resolution of the level sensor may be mainly depend on linearity of frequency sweep. For a linear frequency sweep. the proposed synthesizer employs a phase-locked loop using prescalars and a high speed digital PLL chip. The measured results show that the linear frequency sweep range is from 10 GHz to 11 GHz and the output power of the synthesizer is minium 7 dBm. and the phase noise is about -80 dBc/Hz at 100 KHz offset from 11 GHz.