• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.6
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• pp.477-483
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• 2020

This study proposes a DQ synchronous reference frame model of a series-parallel tuned inductive power transfer (SP-IPT) system. The wireless power transmission system experiences control difficulty because the transmitter-side controller cannot directly measure the receiver-side load voltages and currents. Therefore, a control-oriented circuit model that shows the dynamics of the IPT system is required to achieve a well-behaved controller. In this study, an equivalent circuit model of the SP-IPT system in a synchronously rotating reference frame is proposed using the single-phase DQ transformation technique. The proposed circuit model is helpful in modeling the dynamics of the voltages and currents of the transmitter- and receiver-side resonant tanks and loads. The proposed circuit model is evaluated using frequency- and time-domain simulation results.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.271-275
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• 2014

A New Single Phase Active Power Filter Controller is proposed using Rotating Synchronous Frame d-q transformation. Instantaneous Active Power is calculated using d-q transformation. Average Value of Instantaneous Active Power is obtained using Low Pass Filter. Because power factor is corrected, source current is in phase with source voltage. Amplitude of source current is calculated using single phase power formula. Reference signal of compensated current of Active power filter is obtained from source current reference signal minus load current. Simulation is performed using hysteresis current controller in proposed new controller. Simulation result shows that because active power filter compensates load current, source current is in phase with source voltage and source current is sinusoidal. And Hilbert transformer is builded using all pass filter.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.83-87
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• 2015

This paper presents a simple notch filter, which is so suitable for three-phase unbalanced and distorted power line. In the d-q synchronous transformation, three-phase unbalanced and distorted voltages generate lots of ripple voltages on d-q axes. The ripples make disturbances on controllers such as PLL of phase tracking. Unbalanced state makes ripple of double the frequency of power line. Odd harmonics 5th and 7th on the line make even 4th and 6th ripples on d-q axes due to the rotating reference frame, respectively. Cascaded two comb filters, delay lines 1/4T and 1/8T, are adopted for the ripple rejection. The filter rejects harmonics 2nd, 4th, 6th, 10th and so on. They are very effective to remove the ripples of both unbalance and distortion. The filter, implemented by two FIFOs on an experimental system, is adopted on a PLL controller of power line phase tracking. Through the simulation and experimental results, performance of the proposed comb filter has been validated.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.1
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• pp.29-37
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• 2012

A simple and effective dead time compensation scheme for a PWM inverter-fed permanent magnet synchronous motor (PMSM) drive using the model reference adaptive control (MRAC) and coordinate transformation is presented. The basic concept is to first transform a time-varying disturbance caused by the dead time and inverter nonlinearity into unknown constant or slowly-varying one by the coordinate transformation, and then use the MRAC design technique to estimate this parameter in the stationary reference frame. Since the MRAC scheme is a suitable way of estimating such a parameter, the control performance can be significantly improved as compared with the conventional observer-based method tracking time-varying parameters. In the proposed scheme, the disturbance voltage caused by the dead time is effectively estimated and compensated by on-line basis without any additional circuits nor existing disadvantages as in the conventional methods. The asymptotic stability is proved and the effectiveness of the proposed scheme is verified.

• Journal of Power Electronics
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• v.17 no.2
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• pp.533-541
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• 2017

This paper presents a novel Parameter-Independent Fictive-Axis (PIFA) approach for the Voltage-Oriented Control (VOC) algorithm used in grid-tied single-phase inverters. VOC is based on the transformation of the single-phase grid current into the synchronous reference frame. As a result, an orthogonal current signal is needed. Traditionally, this signal has been obtained from fixed time delays, digital filters or a Hilbert transformation. Nevertheless, these solutions present stability and transient drawbacks. Recently, the Fictive Axis Emulation (FAE) VOC has emerged as an alternative for the generation of the quadrature current signal. FAE requires detailed information of the grid current filter along with its transfer function for signal creation. When the transfer function is not accurate, the direct and quadrature current components present steady-state oscillations as the fictive two-phase system becomes unbalanced. Moreover, the digital implementation of the transfer function imposes an additional computing burden on the VOC. The PIFA VOC presented in this paper, takes advantage of the reference current to create the required orthogonal current, which effectively eliminates the need for the filter transfer function. Moreover, the fictive signal amplitude and phase do not change with a frequency drift, which results in an increased reliability. This yields a fast, linear and stable system that can be installed without fine tuning. To demonstrate the good performance of the PIFA VOC, simulation and experimental results are presented.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1005-1011
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• 2015

This paper proposes the DC offset compensation algorithm with fast response to the sensed grid voltage in the single-phase grid connected inverter. If the sensor of the grid voltage has problems, the DC offset of the grid voltage can be generated. This error must be resolved because the DC offset can generate the estimated grid frequency error of the phase-locked loop (PLL). In conventional algorithm to compensate the DC offset, the DC offset is estimated by integrating the synchronous reference frame d-axis voltage during one period of the grid voltage. The conventional algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage is required. the proposed algorithm has fast dynamic response because the DC offset is consecutively estimated by transforming the d-axis voltage to synchronous reference frame without monitoring one cycle time of the grid voltage. The proposed algorithm is verified from PSIM simulation and the experiment.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.3
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• pp.275-284
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• 1999

Unbalanced source voltage in the 3-phase power system is decomposed into positive, negative and zero sequence c components. Also, assuming there is no neutral path in the system, the zero sequence component is not shown on the l load side. Therefore, in the unbalanced power system without neutral path. it is possible to provide balanced voltage to t the load side by compensating negative sequence component and also to regulate the voltage amplitude by controlling t the positive sequence component. In addition, the symmetrical components due to voltage unbalance can be effectively d detected on the synchronous reference frame by using dlongleftarrowq transformation. In this paper, an algorithm not only c compensating unbalanced source voltage by canceling the negative sequence component on the synchronous reference f frame but also maintaining load voltages constantly is proposed. Also a novel method for phase angle detection s synchronized by positive sequence component under unbalanced source voltage is suggested and this detected phase a angle is used for d-q transformation. The performances and characteristics of the proposed compensating system are a analyzed by simulation and verified through experimental results.

• Journal of Institute of Control, Robotics and Systems
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• v.9 no.12
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• pp.1001-1008
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• 2003

A time-delay compensation method for vector control system is proposed that can compensate for voltage and current distortions resulting from a time delay in the overall system due to the low pass filter, hysteresis control inverter, microprocessor program computation time, and so on. The proposed scheme estimates the time delay using the difference between the Q-axis stator current command and the time-delayed actual Q-axis stator current in a synchronous reference frame, then compensates the time delay in the voltage and current using the angular displacement of a DQ transformation. Accordingly, the proposed scheme can accurately compensate for the time delay related to the overall system, thereby significantly improving the performance of the vector control system, as verified by simulation and experiment.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1334-1344
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• 2014

A novel single phase Phase-Locked Loop (PLL) is proposed in this paper to accurately and rapidly estimate the instantaneous phase angle of a grid. A conjugate rotating vector pair is proposed and defined to synthesize the single phase signal in the stationary reference frame. With this concept, the proposed PLL innovatively sets one phase input of the PARK transformation to a constant zero. By means of a proper cancellation, a zero steady state phase angle estimation error can be achieved, even under magnitude and frequency variations. The proposed PLL structure is presented together with guidelines for parameters adjustment. The performance of the proposed PLL is verified by comprehensive experiments. Satisfactory phase angle estimation can be achieved within one input signal cycle, and the estimation error can be totally eliminated in four input cycles for the most severe conditions.