• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.178-181
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• 2005

This paper presents a synchronous rectifier in a LLC half bridge topology. The proposed synchronous rectifier is used to a current driven synchronous rectifier(SR). If FET is driven without dead times. Voltage driven synchronous rectifier may introduce voltage and current surge during the zero dead times. To solve this problem, we propose to use modified current driven synchronous rectifier. Finally, the prototype is built and comparison on the current and voltage driven synchronous rectifier(SR).

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.295-297
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• 2005

This paper presents a novel current driving method for the synchronous rectifier (SR) in a Flyback topology. The proposed current driven synchronous rectifier features low Power loss, good performance and the gate voltage of FET in the synchronous rectifier is easily controlled by zener voltage. The proposed SR driving method is implemented in a 200W Flyback converter with 400Vdc input and achieved excellent performance at full load.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1395-1397
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• 2005

This paper presents a novel current driving method for the synchronous rectifier(SR) in a flyback topology. The proposed current driven synchronous rectifier features low power loss, good performance and the gate voltage of FET in the synchronous rectifier is easily controlled by resistor ratio. The proposed SR driving method is implemented in a 200W Flyback converter with 400Vdc input and achieved excellent performance at full load.

• 전력전자학회논문지
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• 제11권4호
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• pp.361-370
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• 2006

단일단 단일스위치 통기정류기형 플라이백 컨버터를 제안한다. 제안된 단일단 단일스위치에 의해 역률이 개선되었으며 IEC 61000-3-2의 고조파 전류 요구조건을 만족한다. Flyback 컨버터의 경우 2 차 측 정류용 다이오드로 사용되는 쇼트키 다이오드의 전압 강하에 의한 전력손실이 크며, 이러한 전력 손실을 줄이기 위해 정류용 다이오드를 대신하여 도통 저항이 작은 MOSFET을 사용함으로써 전력손실을 줄일 수 있으며 이를 동기정류기 (SR : Synchronous Rectifier)라 한다. 제안된 동기 정류기는 MOSFET의 드레인 소스간의 전압 강하를 이용하여 동작하는 VDSR(Voltage Driven Synchronous Rectifier)이며 효율 향상을 목적으로 한다. 본 논문에서 제안한 단일단 단일스위치 동기정류기형 플라이백 컨버터는 출력 전력 85W (l2V /7.1A)에 적용되었으며 실험결과를 통해 확인할 수 있다.

• 전력전자학회논문지
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• 제9권2호
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• pp.134-141
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• 2004

본 논문은 DC/DC 컨버터의 효율을 개선하기 위해 동기정류방식을 제시하였다. 제안된 동기정류 방식은 single winding self-driven synchronous rectification(SWSDSR)로서 1차측은 Push-Pull topology를 사용하였다. 특히 이 방식은 데드타임구간에도 동기정류 스위치를 온 시켜서 효율을 개선 할 수 있다. 최종적인 시뮬레이션과 실험 결과는 자기구동 동기정류(SDSR) 방식과 보조권선을 이용한 자기구동 동기정류(SWSDSR) 방식의 효율에 관한 비교와 해석을 보여준다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 F
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• pp.2016-2019
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• 1997

To solve the low efficiency problem of low-voltage power supplies, it has been studied to replace the schottky barrier diode with the MOSFET synchronous rectifier. In this paper, Phase Shift-Controlled Clamp Mode Zero Voltage Switching-Multi Resonant Converter with Synchronous Rectifier (PSC CM ZVS-MRC with SR) is presented to achieve high efficiency in low-voltage power supplies. The characteristics analysis of synchronous rectifier is established by using the MOSFET equivalent circuit and efficiency comparison is established between the Synchronous Rectifier and the schottky barrier diode. To verify the validity of the analysis, 33W(3.3V, 10A) PSC CM ZVS-MRC with self-driven synchronous rectifier at switching frequency of 1MHz is designed and tested. And it is confirmed that the experimental results are well consistent with the theoretical results. The maximum efficiency of the converter is 83.4% at full load, which is 3.3% higher than conventional schottky diode rectification.

• 조명전기설비학회논문지
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• 제30권1호
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• pp.79-86
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• 2016

In this paper, we propose a current-driven synchronous rectifier driver circuit for LLC resonant half-bridge converters. The proposed driver circuit detects a relatively low current in the primary side of the transformer although a large current is flowing in the secondary side. Due to this feature, the driver circuit has a simple circuit structure and stabilizes the switching operation with a logic-level switching voltages for the synchronous rectifier. The operation and performance of the proposed driver circuit are confirmed with a prototype of 1kW class LLC resonant half-bridge converter. The experimental results proved that the proposed synchronous rectifier driver method improves the power conversion efficiency by around 1% and reduces the internal power loss by 17W.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제55권9호
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• pp.472-477
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• 2006

This paper presents a new voltage/current mixed method for driving synchronous rectifiers (SR) adapted to the flyback topology. The synchronous rectifier driven by the proposed voltage/current mixed method can operate at a wide load range with high efficiency. The gate voltage of MOSFET in the synchronous rectifier can be easily controlled by changing the ratio of resistors, irrespective of a line and load fluctuation. A 200W (12V/17A) prototype converter was built and an efficiency of 93% was measured at 10A load current.

• Journal of Power Electronics
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• 제16권1호
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• pp.121-132
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• 2016

In this paper, high-efficiency design methodology of a zero-voltage-switching full-bridge (ZVS-FB) pulse width modulation (PWM) converter for server-computer power supply is discussed based on self-driven synchronous rectifier (SR) performance. The design approach focuses on rectifier conduction loss on the secondary side because of high output current application. Various-number parallel-connected SRs are evaluated to reduce high conduction loss. For this approach, the reliability of gate control signals produced from a self-driver is analyzed in detail to determine whether the converter achieves high efficiency. A laboratory prototype that operates at 80 kHz and rated 1 kW/12 V is built for various-number parallel combination of SRs to verify the proposed theoretical analysis and evaluations. Measurement results show that the best efficiency of the converter is 95.16%.

• 전력전자학회논문지
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• 제18권4호
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• pp.312-321
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• 2013

In this paper, high efficiency control method for flyback inverter with synchronous rectifier(SR) based on photovoltaic AC modules is proposed. In this control method, the operation of SR is classified according to the voltage spike across main switch SP. When the voltage spike across SP is lower than the rating voltage of SP, the operation of active clamp circuit is interrupted for reducing the switching loss of auxiliary switch. In this time, the SR is operated for soft-switching of SP. When the voltage spike across Sp is higher than the rating voltage of SP, the operation of active circuit is activated for reducing the voltage spike. The SR is operated for reducing the conduction loss of secondary output diode. Thus, a switching loss of the main switch can be reduced in low power region, and weighted-efficiency can be improved. A theoretical analysis and the design principle of the proposed method are provided. And validity is confirmed through simulation and experimental results.