• 한국정밀공학회지
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• 제21권2호
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• pp.100-107
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• 2004

The development of a Web-based powertrain performance simulation system is introduced. The development approach of system architecture and each module is introduced along with the H/W and S/W used. The interface with all users is developed via a JAVA Applet. The powertrain modeling and other job history data of a user is managed systematically on the server by database to increase the reusability of the data. A self-developed program using object-oriented programming is used as a solver for the performance simulation. The graph tool for the analysis of simulation results has the collaboration support developed based on JAVA so that synchronous users can view the same result. As a result, the powertrain simulation is possible only with Web-browser for the user and the collaboration support among the relevant engineers is possible.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.268-271
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• 2001

This paper presents observer-based on-line overload monitoring scheme for a PMSM(Permanent Magnet Synchronous Motor) drive system. Proposed scheme is to monitor overload status of motor drive system at remote place. The drive system is previously installed on main system and has no communication function. Proposed scheme consists of intelligent sensing head and monitoring part. Intelligent sensing head acquire motor 3-Phase currents and transmit data to monitoring part over serial communication interface. Monitoring part estimates motor speed using state observer. By comparing estimated speed with reference speed, we can detect motor fault. In this scheme observed information must coded and transmitted over a digital communication channel with finite capacity. We consider communication constraint as time delay and we design discrete-time observer. The proposed scheme is tested on the actual drive system.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.152.4-152
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• 2001

We investigate, in this paper, the use of FPGA(Field Programmable Gate Array) architectures for real-time processing of digital linescan camera. The use of FPGAS for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. This new synchronous unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image ...

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2003년도 춘계학술대회 논문집
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• pp.1747-1750
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• 2003

The development of a Web-based powertrain performance simulation system is introduced. The development approach of system architecture and each module is introduced along with the H/W and S/W used. The interface with all users is developed via a JAVA applet. The powertrain modeling and other job history data of a user is managed systematically on the server by database to increase the reusability of the data. A self-developed program using object-oriented programming is used as a solver for the performance simulation. The graph tool for the analysis of simulation results has the collaboration support developed based on JAVA so that synchronous users can view the same result. As a result, the powertrain simulation is possible only with Web-browser for the user and the collaboration support among the relevant engineers is possible.

• 대한의용생체공학회:의공학회지
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• 제17권2호
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• pp.179-188
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• 1996

A clinically oriented 32-channel electroencephalogram (EEG) and evoked potential (EP) mapping system has been developed EEG and EP signals acquired from 32-channel electrodes attached on the heroid surface are amplified by a pre-amplifier which is separated from main amplifier and is located near the patient to reduce signal attenuation and noise contamination between electrodes and the amplifier. The amplified signals are further amplified by a main amplifier where various filtering and gain contr61 are achieved An automatic artifact rejection scheme is employed using neural network-based EEG and artifact classifier, by which examination time is substantially reduce4 The continuously measured EEG sigrlals are used for spectral mapping, and auditory and visual evoked potentials measured in synchronous to the auditory and visual stimuli are used for temporal evoked potential mapping. A user-friendly graphical interface based on the Microsoft Window 3.1 is developed for the operation of the system. Statistical databases for comparisons of group and individual are included to support a statistically-based diagnosis.

• 한국우주과학회:학술대회논문집(한국우주과학회보)
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• 한국우주과학회 2004년도 한국우주과학회보 제13권2호
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• pp.344-346
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• 2004

KOMPSAT-2 (Korea Multi Purpose Satellite 2) which is scheduled to launch in 2005 year will communicate with KARI TTC (Tracking, Telemetry, and Command) station flying along sun synchronous orbits (685 km). The command from KARI TTC passes S-band omni-antenna, RF assembly, and transponder and finally reachs OBC (On Board Computer). The telemetry from KOMPSAT-2 arrives at KARI TTC through inverse procedure. In this paper, RF compatibility test between KOMPSAT-2 and KARI TTC station is demonstrated. RF interface for this test was established through real space and uplink signal test and downlink signal test and uplink & downlink signal test were performed.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제53권2호
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• pp.123-128
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• 2004

Recently with the development of power switching device and DSP which has perip -heral devices to control AC servo system, the servo technology has met a new development opportunity. In this study, a DSP based AC servo system with a 3-phase PMSM is proposed. The newly produced DSP TMX320F2812 version C which has the performance of fast speed, 150MIPS, and rich peripheral interface is used. Also space vector pulse width modulation (SVPWM) and the digital PI control are implemented to the servo control system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 B
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• pp.1450-1452
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• 2005

AC Servo system has been implemented to semiconductor equipments system for their requirements of the high resolution control. This paper is based on the newly produced DSP TMS320F2812 which has the performance of fast processing speed, 150 MIPS, and rich peripheral interface. The implemented system has been developed for the position control that also has speed and current control as inner loops. The controller implemented a high precision position control system with SVPWM and digital PI control and using high resolution rotary encoder.

• 한국시뮬레이션학회논문지
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• 제7권1호
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• pp.69-83
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• 1998

In this paper, we present the results of simulation by running parallel VHDL simulation on typical MPP(Massively Parallel Processor) systems such as IBM SP2 and SGI Origin 2000. Parallel simulation uses the synchronous protocol and parallel program is implemented using MPI(Message Passing Interface) based on message passing model, so that it can urn on any parallel programming environment which supports MPI, a standard communication library. And then GVT(Global Virtual Time) computation for parallel simulation is based on the global broadcasting with MPI＿Bcast(), which is a standard function in MPI and piggybacking. Our benchmark exhibits that as size of VHDL grows, the parallel simulation has a better performance compared with the sequential simulation. In addition, we also show the results of comparison between IBM SP2 and SGI Origin 2000 by applying the same application to those indirectly.

• 대한전자공학회논문지SD
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• 제42권4호
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• pp.9-18
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• 2005

본 논문은 OCP(Open Core Protocol)에 호환되는 파이프라인 구조를 가진 시스템 버스와 MPEG 시스템에 적합한 메모리 버스로 구성된 계층 구조를 가지는 새로운 동기 세그먼트 버스를 제안한다. 이 구조는 MPEG 시스템의 모바일 제품에 사용되는 영상 데이터 처리를 위한 메모리 인터페이스에 기반을 둔 버스 구조와 멀티 마스터와 멀티 슬레이브를 사용하여 고성능의 다중 처리를 위한 양방향 다중 버스 구조(hi-direction multiple bus architecture)를 가진다. 효율적인 데이터 처리를 위하여 파이프라인 스테이지와 결합된 마스터와 슬레이브의 주소번지가 latency를 결정하며, 시스템의 특성에 따라서 각각의 IP 코어를 배치하였다. 제안된 버스는 저전력 구현을 위하여 세그먼트 버스 구조를 가지고, 멀티미디어 SoC 시스템의 성능 저하 없이 다중 작업이 가능한 구조를 가지며 확장이 가능하다. 제안된 버스 구조는 AMBA와 비교하였을 때 bandwidth는 3.7배 증가하였고 latency는 0.25배 감소하였다.