• Title/Summary/Keyword: Synchronization algorithm

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A study for improvement of Recognition velocity of Korean Character using Neural Oscillator (신경 진동자를 이용한 한글 문자의 인식 속도의 개선에 관한 연구)

  • Kwon, Yong-Bum;Lee, Joon-Tark
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2004.04a
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    • pp.491-494
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    • 2004
  • Neural Oscillator can be applied to oscillatory systems such as the image recognition, the voice recognition, estimate of the weather fluctuation and analysis of geological fluctuation etc in nature and principally, it is used often to pattern recoglition of image information. Conventional BPL(Back-Propagation Learning) and MLNN(Multi Layer Neural Network) are not proper for oscillatory systems because these algorithm complicate Learning structure, have tedious procedures and sluggish convergence problem. However, these problems can be easily solved by using a synchrony characteristic of neural oscillator with PLL(phase-Locked Loop) function and by using a simple Hebbian learning rule. And also, Recognition velocity of Korean Character can be improved by using a Neural Oscillator's learning accelerator factor η$\_$ij/

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Design of High-Speed Correlator for a Binary CDMA (Binary CDMA를 위한 고속 코릴레이터 설계)

  • 구군서;정우경;문장식;류승문;이용석
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.787-790
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    • 2003
  • This paper describes a high speed correlator that can acquire synchronization quickly. The existing addition algorithm is a binary adder tree architecture that will result in extremely slow speed of operation due to many levels of logic required for computation of correlation[2][3]. This paper suggests the new various architectures, which are systolic array architecture, simple pipeline architecture and block systolic array architecture[4][5]. The acquisition performance of the proposed architectures is analyzed and compared with the existing architecture. The comparison results show that the systolic array architecture and the block systolic array architecture reduce the timing delay up to 73% and 31%, respectively. And the results show that the simple pipeline architecture reduces the timing delay up to 53%..

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PARALLEL IMPLEMENTATION OF HYBRID ITERATIVE METHODS FOR NONSYMMETRIC LINEAR SYSTEMS

  • Yun, Jae-Heon;Kim, Sang-Wook
    • Journal of applied mathematics & informatics
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    • v.4 no.1
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    • pp.1-16
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    • 1997
  • In this paper we study efficient parallel implementation for hybrid iterative methods BICGSTAB and BICGSTAB $(\ell)$ with ${Well}=2$ on the CRAY C90 and the efficiency of their parallel performance is evaluated. numerical experiments suggest that on the CRAY C90 a parallel inner product algorithm called PDOTB be used for the par-allelization of hybrid iterative methods containing sensitive values of inner products. Lastly it is shown that the number of iterations in which parallel hybrid iterative methods satisfy a certain convergence criterion depends on the number of processors to be used.

Integer-Pel Motion Estimation for HEVC on Compute Unified Device Architecture (CUDA)

  • Lee, Dongkyu;Sim, Donggyu;Oh, Seoung-Jun
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.6
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    • pp.397-403
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    • 2014
  • A new video compression standard called High Efficiency Video Coding (HEVC) has recently been released onto the market. HEVC provides higher coding performance compared to previous standards, but at the cost of a significant increase in encoding complexity, particularly in motion estimation (ME). At the same time, the computing capabilities of Graphics Processing Units (GPUs) have become more powerful. This paper proposes a parallel integer-pel ME (IME) algorithm for HEVC on GPU using the Compute Unified Device Architecture (CUDA). In the proposed IME, concurrent parallel reduction (CPR) is introduced. CPR performs several parallel reduction (PR) operations concurrently to solve two problems in conventional PR; low thread utilization and high thread synchronization latency. The proposed encoder reduces the portion of IME in the encoder to almost zero with a 2.3% increase in bitrate. In terms of IME, the proposed IME is up to 172.6 times faster than the IME in the HEVC reference model.

Determination of Optimal Phase Split and Offset for the Synchronization of Traffic Signals in the CBD of Seoul (서울시(市) 신호체제의 적정 phase split 과 연쇄화를 위한 최적 offset)

  • Park, Gyeong-Su
    • Journal of Korean Institute of Industrial Engineers
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    • v.3 no.1
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    • pp.49-53
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    • 1977
  • The coordinated control of the traffic signals of adjacent intersections can reduce delays, relative number of stops and congestions in the coordinated traffic area. The road capacity can be increased to a certain extend because the stopping and starting of vehicles facing red traffic lights can be avoided in many instances due to the progression established along an artery. However, if traffic centers or leaves the main flow in irregular volumes on the intermediate road section, a coordination of traffic signals is unnecessary and may even be harmful. Therefore, a computer simulation model to simulate and predict the effectiveness of a synchronized traffic signal system in the CBD of Seoul was developed and alternative policy variables, such as cycle time, offsets, phase splits, to be fed into the simulation model had to be generated. This is a report of (1) the development of a heuristic algorithm for the determination of phase splits when there are amber periods specifically reserved for left turns and (2) the computerization of time-space diagramming.

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Authentication Protocol with OTP Generation and Synchronization using Stream algorithm (스트림 알고리즘을 이용한 OTP 생성 및 동기화 인증 프로토콜)

  • Lee, Jang-Chun;Lee, Hoon-Jae;Kim, Tae-Yong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2007.10a
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    • pp.305-308
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    • 2007
  • 현재 네트워크상에 사용자를 인증하는 부분은 시스템 보안상으로 아주 중요한 역할을 하고 있다. 공개된 네트워크에서는 개인의 중요한 프라이버시 정보를 보호하기 위해 인증 절차를 거치게 된다. 이러한 인증 방법에는 간단한 Identity/Password 인증부터 복잡한 생채 공학 인증까지 다양한 기술들이 존재 한다. 최근 금융보안업계가 주축이 되어 일회용패스워드(OTP : One Time Password) 인증 시스템을 활용하기 위한 기술적 시도 및 개발이 활발히 이루어지고 있다. 일회용 패스워드는 사용자가 인증 받고자 할 때 새로운 패스워드를 생성하고 사용 후 버린다는 구조를 가지고 있다. 이는 매번 같은 패스워드를 사용했을 때 발생하는 보안 문제점을 해결할 수 있다. 그러나 OTP 인증 방법에도 여러 가지 공격 방법에 취약한 문제점들이 노출되어 있다. 본 논문은 기존의 인증 프로토콜 문제점을 개선하고 크기가 작은 스트림 알고리즘을 이용하여 스마트카드에서 사용 가능한 새로운 인증 프로토콜을 제안한다.

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Implementation of Synchronization Algorithm for Networked Multi-Motors (네트워크기반 복수전동기의 동기제어알고리즘 구현)

  • Lee Hong-Hee;Jung Eui-Heon;Kim Jung-Hee
    • Proceedings of the KIPE Conference
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    • 2002.07a
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    • pp.270-273
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    • 2002
  • 복수구동장치를 사용하여 작업을 수행하는 시스템은 동기화를 위해 기계적인 제한조건을 두고 운용하는 경우 지속적인 유지보수가 요구되고 작업 정밀도가 떨어진다 이러한 단점을 보완하기 위해 개별적인 구동장치의 제어루프 외부에 동기화를 위한 제어루프를 추가하는 방법이 제안되었다. 본 논문에서는 CAN(Controller Area Network)으로 연결된 두 대의 서보앰프를 구동하여 주어진 작업을 수행하는 경우 외란과 내부 파라미터 변동에 강인한 $H^{\infty}$ 제어기를 설계하고 이를 이용하여 동기제어 알고리즘을 구현하고자한다.

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Performance improvement of TCP Reno congestion control algorithm using end-to-end estimation of forward/backward delay variation (종단간 순방향/역방향 전송 지연에 따른 TCP Reno 혼잡제어 알고리즘 성능향상)

  • Han, Kyu-Hyeong;Kim, Eun-Gi
    • Proceedings of the Korea Information Processing Society Conference
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    • 2005.11a
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    • pp.1295-1298
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    • 2005
  • 기존 TCP Reno 의 혼잡 제어는 트래픽에 수동적으로 동작하는 방법으로서 혼잡이 이미 발생한 상태에서 동작하게 되므로 발생 시점의 라우터 버퍼는 이미 최대치에 도달해 있게 된다. 따라서 이후에 도착하는 모든 패킷은 폐기되므로 이 패킷들을 전송한 모든 송신원은 거의 동시에 윈도우 크기를 줄이는 Slow-start 단계에 들어가게 되어 일시적으로 링크 사용률이 떨어지는 전역 동기화(global synchronization)가 발생하게 된다. 이러한 문제를 해결하기 위해서는 네트워크의 혼잡이 발생하기 전에 능동적으로 대처하는 방안이 필요하다. 본 논문에서는 새로운 RTT 계산 알고리즘인 순방향/역방향 전송지연 알고리즘을 이용하여 네트워크의 혼잡을 미리 예측하고 네트워크 혼잡에 능동적으로 대처할 수 있는 새로운 알고리즘을 제안한다. 본 논문에서는 리눅스(Linux) 커널(Kernel)의 TCP Reno 의 흐름제어 및 혼잡제어를 수정하여 네트워크 혼잡에 능동적으로 대처 할 수 있는 새로운 TCP Reno 를 설계, 구현하였다.

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Fault Detection in the Semiconductor Etch Process Using the Seasonal Autoregressive Integrated Moving Average Modeling

  • Arshad, Muhammad Zeeshan;Nawaz, Javeria Muhammad;Hong, Sang Jeen
    • Journal of Information Processing Systems
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    • v.10 no.3
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    • pp.429-442
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    • 2014
  • In this paper, we investigated the use of seasonal autoregressive integrated moving average (SARIMA) time series models for fault detection in semiconductor etch equipment data. The derivative dynamic time warping algorithm was employed for the synchronization of data. The models were generated using a set of data from healthy runs, and the established models were compared with the experimental runs to find the faulty runs. It has been shown that the SARIMA modeling for this data can detect faults in the etch tool data from the semiconductor industry with an accuracy of 80% and 90% using the parameter-wise error computation and the step-wise error computation, respectively. We found that SARIMA is useful to detect incipient faults in semiconductor fabrication.

A Study on the Power Monitoring System using GPS for Accurate Time Synchronization (GPS 정밀시각동기를 이용한 전력계통 모니터링 시스템에 관한 연구)

  • 김혁수;전성준;김기택
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.285-285
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    • 2000
  • A continuous and reliable electrical energy supply is the objective of any power system operation. A transmission line is the part of the power system where faults are most likely to happen. This paper describes the use of wavelet transform for analyzing power system fault transients in order to determine the fault location. Synchronized sampling was made possible by precise time receivers based on GPS time reference, and the sampled data were analyzed using wavelet transform. This paper describes a fault location monitoring system and fault locating algorithm with GPS, DSP processor, and data acquisition board, and presents some experimental results and error analysis.

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