• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.7
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• pp.2891-2903
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• 2020

Phase-generated carrier (PGC) demodulation algorithm is the main demodulation methods in Fiber-optic interferometric sensors (FOISs). The conventional PGC demodulation algorithms are influenced by the carrier phase delay between the interference signal and the carrier signal. In this paper, an automatic carrier phase delay synchronization (CPDS) algorithm based on orthogonal phase-locked technique is proposed. The proposed algorithm can calculate the carrier phase delay value. Then the carrier phase delay can be compensated by adjusting the initial phase of the fundamental carrier and the second-harmonic carrier. The simulation results demonstrate the influence of the carrier phase delay on the demodulation performance. PGC-Arctan demodulation system based on CPDS algorithm is implemented on SoC. The experimental results show that the proposed algorithm is able to obtain and eliminate the carrier phase delay. In comparison to the conventional demodulation algorithm, the signal-to-noise and distortion ratio (SINAD) of the proposed algorithm increases 55.99dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.99-108
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• 1999

In this paper, we propose $\pi$/4 QPSK scheme with block modulation algorithm, which can reduce preamble in order to transmit ATM cell efficiently in the uplink channel of LMDS, and also designed a new carrier recovery circuit which can improve carrier synchronization performance of block demodulation algorithm. The $\pi$/4 QPSK scheme employing the proposed block modulation algorithm achieved efficient frame transmission by making use of a few preamble when carrier synchronization, symbol timing synchronization and slot timing synchronization were performed by burst data of ATM cell in LMDS environment. For performance evaluation of the proposed method, a simulation analyzing the variation of carrier synchronization, symbol timing synchronization and slot timing synchronization using LMDS environment and burst mode condition was executed. In the simulation, the proposed method showed a good performance even though the reduced preamble as a few aspossible when carrier synchronization, symbol timing synchronization and slot timing synchronization is performed.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.857-860
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• 1999

It is made possible a removal of the preamble for carrier recovery and symbol-timing recovery by storing a burst in memory with low overhead QPSK demodulation and this demodulation method also effects frame efficiency improved by processed synchronization performance. In this paper, we have proposed that new algorithm for arc-tangent look-up table which transform the input I, Q data by phase. This I, Q data plays an important role in demodulation and makes demodulator with low-overhead by storing a burst in memory. To evaluate proposed new algorithm and symbol-timing recovery method, function simulation and timing verification have been done by using synopsys VHDL tool.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.10 s.89
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• pp.952-960
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• 2004

PSK(Phase Shift Keying) is useful because of the power and spectral efficient modulation. In this paper, no additional hardware will be needed to support various transmit mode in the suggested DSP scheme. We design and implement the synchronization algorithm for M-ary PSK(M=2, 4) demodulator based on DSP scheme, instead of complex analog PSK demodulator. TMS320C6203 is used as DSP. We check the all kinds of waveforms via the graph view window after software programming the emulation on the DSP tool. The result of implementation proves that demodulator using the suggested algorithm has equal performance with demodulator using analog circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1506-1513
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• 2009

This paper presents a synchronization method to determine the exact demodulation time using the MFM Flag of the 18000-3 PJM mode, along with the hardware structure to implement the proposed method. The proposed system detects an incipient peak using ITS(Initial Time Selector) and a correlator and achieves the final synchronization via identifying the peak position from the comparison of the outputs of two followed additional correlators. The peak detection algorithm and the choice of the templates of the correlators are described. Simulation results show that the proposed system performs successfully in noisy environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.1A
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• pp.73-81
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• 2012

In this paper, we propose a high-speed synchronization method for Digital Radio Mondiale (DRM) receivers. In order to satisfy the high-speed synchronization requirement of DRM receivers, the proposed method eliminate the initial sampling frequency synchronization process in conventional synchronization methods. In the proposed method, sampling frequency tracking is performed after integer frequency synchronization and frame synchronization. Different correlation algorithms are applied to detect the first frame of the Orthogonal Frequency Division Multiplexing (OFDM) demodulation symbol with sampling frequency offset (SFO). A frame detection algorithm that is robust to SFO is selected based on the performance analysis and simulation. Simulation results show that the proposed method reduces the time spent for initial sampling frequency synchronization even if SFO is present in the DRM signal. In addition, it is verify that inter-cell differential correlation used between reference cells is roubst to the effect of initial SFO.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2C
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• pp.192-199
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• 2008

In ultra-wideband (UWB) systems, conventionally, the synchronization is to align time phases of a locally generated template and any of multipath components to within an allowable range. However, the synchronization with a low-power multipath component could incur significant performance degradation in receiver operation (e.g., detection) after the synchronization. On the other hand, the synchronization with a high-power multipath component can improve the performance in receiver operation after the synchronization. Generally, the first one among multipath components has the largest power. Thus, the synchronization with the first path component can make better performance than that with low-power component in receiver operation after the synchronization, Based on which, we first propose an optimal decision rule based on a maximum likelihood (ML) approach, and then, develope a simpler suboptimal decision rule for selecting the first path component. Simulation results show that the system has good demodulation performance, which uses new synchronization definition and the proposed decision rules have better performance than that of the conventional decision rule in UWB multipath channels. Between macroblocks in the previous and the current frame. On video samples with high motion and scene change cases, experimental results show that (1) the proposed algorithm adapts the encoded bitstream to limited channel capacity, while existing algorithms abruptly excess the limit bit rate; (2) the proposed algorithm improves picture quality with $0.4{\sim}0.9$dB in average.

• ETRI Journal
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• v.30 no.4
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.290-297
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• 2014

The synchronization of OFDM receiver is consisted of symbol timing offset(STO) estimation in time domain and carrier frequency offset(CFO) estimation in frequency domain. This paper proposes new algorithm for correcting the integer CFO after we have done correcting the STO and partial CFO. ICFO must be corrected, since the ICFO lead to degrade bit error rate(BER) of demodulation performance. The PN sequence has information which is subcarrier order since the modified PN sequence, length is same subcarrier, is used in this paper and is modulated each subcarrier by each chip. Thus the receiver track phase of PN sequence after FFTin order to find the subcarrier frequency offset. The proposed algorithm is faster and more simple than convenient methode as measuring carrier energy.