• Korean Management Science Review
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• v.11 no.1
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• pp.187-196
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• 1994

Time-Space-Time(T-S-T) switching network is modeled as a graceful degrading system. Call blocking probability is defined as a measure of performance. Several performance related measures are suggested under the presence of failure. An optimization model is proposed, which determines optimal values of system parameters of the switching network.

• Journal of Power Electronics
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• v.7 no.3
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• pp.181-190
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• 2007

This paper presents a novel circuit topology of a DC bus line series switch and parallel snubbing capacitor-assisted soft-switching PWM full-bridge inverter type DC-DC power converter with a high frequency planar transformer link, which is newly developed for high performance arc welding machines in industry. The proposed DC-DC power converter circuit is based upon a voltage source-fed H type full-bridge soft-switching PWM inverter with a high frequency transformer. This DC-DC power converter has a single power semiconductor switching device in series with an input DC low side rail and loss less snubbing capacitor in parallel with the inverter bridge legs. All the active power switches in the full-bridge arms and DC bus line can achieve ZCS turn-on and ZVS turn-off transition commutation. Consequently, the total switching power losses occurred at turn-off switching transition of these power semiconductor devices; IGBTs can be reduced even in higher switching frequency bands ranging from 20 kHz to 100 kHz. The switching frequency of this DC-DC power converter using IGBT power modules can be realized at 60 kHz. It is proved experimentally by power loss analysis that the more the switching frequency increases, the more the proposed DC-DC power converter can achieve a higher control response performance and size miniaturization. The practical and inherent effectiveness of the new DC-DC converter topology proposed here is actually confirmed for low voltage and large current DC-DC power supplies (32V, 300A) for TIG arc welding applications in industry.

• ETRI Journal
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• v.31 no.3
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• pp.321-323
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• 2009

A wideband beamforming algorithm for estimating the azimuth angle, elevation angle, velocity, and range using a planar phased radar array with antenna switching is proposed. It uses the time-variant steering vector model. Simulation results illustrating the performance of the proposed beamformer are presented.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.29-32
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• 2000

MPLS stands for “Multi-protocol Label Switching”. It's a layer 3 switching technology aimed at greatly improving the packet forwarding performance of the backbone routers in the Internet or other large networks. We compare the performance of unlabeled IP traffic and labeled IP traffic. In this paper, by varying the packet rate and measuring throughput of the flows we analyze the performance of labeled IP packet traffic and unlabeled IP packet traffic in IP over MPLS.

• Journal of Internet Computing and Services
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• v.4 no.6
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• pp.69-73
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• 2003

ATM and Ethernet are desirable transport mechanisms for the realization MAN(Metropolitan Area Networks). A relatively small sized switching system for MAN based on ATM is proposed and its performance is evaluated in this paper. For the performance evaluation, traffics should be firstly modeled because they are highly bursty. By varing the ratio of VBR traffics, detrimental effect of VBR traffics may be observed. Traffic load at each input port is also varied, From the results of simulation, operation conditions of the system to meet required QoS are obtained.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.307-310
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• 2000

ATM is the switching and multiplexing technology chosen by the ITU-T for the operation of B-lSDN. Basically, ATM technology is designed to combine the reliability of circuit switching with the efficiency and flexibility of packet switching technology. For servicing QoS in IPOA(IP over ATM) when the larger effort is given, it will be the good method that the original QoS benefits having ATM switching have in ATM layer underlying layer. The IETF has recently proposed Differentiated Services framework for provision of QoS. In this paper we analyse performance of two Diffserv mechanism. Threshold Dropping and Priority Scheduling. Threshold Dropping and Priority Scheduling can be regarded as basic mechanisms from which the other mechanisms have been derived. Hence comparative performance of these two mechanisms in providing required QoS is an important issue. In this Paper we carry out a performance comparison of the TD and PS mechanisms with the aim of providing the same level of packet loss to the preferred flow. Our comparison of the TD and PS allows us to determine resultant packet loss for the non-preferred flows as a function of various parameters of the two mechanisms.

• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.4
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• pp.225-233
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• 2010

In this paper, we try to improve the performance of the demand paging loader suggested to use the demand paging way that is not based on operating system. The demand paging switching strategy used in the existing operating system can know the recently used pages by running multi-processing. Then, based on it, some page switching strategies have been made for the recently used pages or the frequently demanded pages. However, the strategies based on operating system cannot be applied in single processing that is not based on operating system because any context switching never occur on the single processing. So, this paper is trying to suggest the demand paging switching strategies that can be applied in paging loader running in single process. In the Return-Prediction-Algorithm, we saw the improved performance in the program that the function call occurred frequently in a long distance. And then, in the Most-Frequently-Used-Page-Remain-Algorithm, we saw the improved performance in the program that the references frequently occurred for the particular pages. Likewise, it had an enormous effect on keeping the memory reduction performance by the demand paging and reducing the running time delay at the same time.

• Korean Management Science Review
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• v.10 no.1
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• pp.139-156
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• 1993

Various ATM switches have been proposed since Asynchronous Transfer Mode (ATM) was recognized as appropriate for implementing broadband integrated services digital network (BISDN). An ATM switching network may be evaluated on two sides : traffic performances (maximum throughput, delay, and packet loss probability, etc.) and structural features (complexity, i.e. the number of switch elements necessary to construct the same size switching network, maintenance, modularity, and fault tolerance, etc.). ATM switching networks proposed to date tend to show the contrary characteristics between structural features and traffic performance. The Knockout Switch, which is well known as one of ATM switches, shows a good traffic performance but it needs so many switch elements and buffers. In this paper, we propose an input and output buffered Knockout Switch for the purpose of reducing the number of switch elements and buffers of the existing Knockout Switch. We analyze the traffic performance and the structural features of the proposed switching architecture through a discrete time Markov chain and compare with those of the existing Knockout Switch. It was found that the proposed architecture could reduce more than 40 percent of switch elements and more than 30 percent of buffers under a given requirement of cell loss probability of the switch.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.2
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• pp.94-102
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• 2004

The digital electronic switching system has some problems, when this system processes OAM(Operation, Administration And Maintenance) messages about the fault, the traffic, the account, and the performance, etc., at the present. One of these problems is that each the module processing these messages in the digital electronic switching system can not process OAM messages out of another digital electronic switching system. Each the module processing these OAM messages, that is, has been programmed in order to process only the OAM message out of the digital electronic switching system mounting itself, not to process the message out of the digital electronic switching system based on another platform. Therefore, we studied on methods that could process OAM messages out of all digital electronic switching systems and, first of all, developed the MGS(Message Gathering System) to be able to accept and process the fault message of OAM messages out of all digital electronic switching systems in real time.