• Title/Summary/Keyword: Switched integrator

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A Single-Bit 2nd-Order CIFF Delta-Sigma Modulator for Precision Measurement of Battery Current (배터리 전류의 정밀 측정을 위한 단일 비트 2차 CIFF 구조 델타 시그마 모듈레이터)

  • Bae, Gi-Gyeong;Cheon, Ji-Min
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.3
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    • pp.184-196
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    • 2020
  • In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for precision measurement of current flowing through a secondary cell battery in a battery management system (BMS). The proposed modulator implements two switched capacitor integrators and a single-bit comparator with peripheral circuits such as a non-overlapping clock generator and a bias circuit. The proposed structure is designed to be applied to low-side current sensing method with low common mode input voltage. Using the low-side current measurement method has the advantage of reducing the burden on the circuit design. In addition, the ±30mV input voltage is resolved by the ADC with 15-bit resolution, eliminating the need for an additional programmable gain amplifier (PGA). The proposed a single-bit 2nd-order delta-sigma modulator has been implemented in a 350-nm CMOS process. It achieves 95.46-dB signal-to-noise-and-distortion ratio (SNDR), 96.01-dB spurious-free dynamic range (SFDR), and 15.56-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 400 for 5-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 670×490 ㎛2 and 414 ㎼, respectively.

Improved Programmable LPF Flux Estimator with Synchronous Angular Speed Error Compensator for Sensorless Control of Induction Motors (유도 전동기 센서리스 제어를 위한 동기 각속도 오차 보상기를 갖는 향상된 Programmable LPF 자속 추정기)

  • Lee, Sang-Soo;Park, Byoung-Gun;Kim, Rae-Young;Hyun, Dong-Seok
    • The Transactions of the Korean Institute of Power Electronics
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    • v.18 no.3
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    • pp.232-239
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    • 2013
  • This paper proposes an improved stator flux estimator through ensuring conventional PLPF to act as a pure integrator for sensorless control of induction motors. Conventional PLPF uses the estimated synchronous speed as a cut-off frequency and has the gain and phase compensators. The gain and phase compensators are determined on the assumption that the estimated synchronous angular speed is coincident with the real speed. Therefore, if the synchronous angular speed is not same as the real speed, the gain and phase compensation will not be appropriate. To overcome the problem of conventional PLPF, this paper analyzes the relationship between the synchronous speed error and the phase lag error of the stator flux. Based on the analysis, this paper proposes the synchronous speed error compensation scheme. To achieve a start-up without speed sensor, the current model is used as the stator flux estimator at the standstill. When the motor starts up, the current model should be switched into the voltage model. So a stable transition between the voltage model and the current model is required. This paper proposes the simple transition method which determines the initial values of the voltage model and the current model at the transition moment. The validity of the proposed schemes is proved through the simulation results and the experimental results.

Design of Low Power Sigma-delta ADC for USN/RFID Reader (USN/RFID Reader용 저전력 시그마 델타 ADC 변환기 설계에 관한 연구)

  • Kang, Ey-Goo;Hyun, Deuk-Chang;Hong, Seung-Woo;Lee, Jong-Seok;Sung, Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.9
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    • pp.800-807
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    • 2006
  • To enhance the conversion speed more fast, we separate the determination process of MSB and LSB with the two independent ADC circuits of the Incremental Sigma Delta ADC. After the 1st Incremental Sigma Delta ADC conversion finished, the 2nd Incremental Sigma Delta ADC conversion start while the 1st Incremental Sigma Delta ADC work on the next input. By determining the MSB and the LSB independently, the ADC conversion speed is improved by two times better than the conventional Extended Counting Incremental Sigma Delta ADC. In processing the 2nd Incremental Sigma Delta ADC, the inverting sample/hold circuit inverts the input the 2nd Incremental Sigma Delta ADC, which is the output of switched capacitor integrator within the 1st Incremental Sigma Delta ADC block. The increased active area is relatively small by the added analog circuit, because the digital circuit area is more large than analog. In this paper, a 14 bit Extended Counting Incremental Sigma-Delta ADC is implemented in $0.25{\mu}m$ CMOS process with a single 2.5 V supply voltage. The conversion speed is about 150 Ksamples/sec at a clock rate of 25 MHz. The 1 MSB is 0.02 V. The active area is $0.50\;x\;0.35mm^{2}$. The averaged power consumption is 1.7 mW.