• Title/Summary/Keyword: Stress current

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Output Inductor Less Phase Shift Full Bridge Converter with Current Stress Reduction Technique for Server Power Application

  • Lee, Woo-Jin;Park, Ki-Bum;Heo, Tae-Won;Moon, Gun-Woo
    • Proceedings of the KIPE Conference
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    • 2008.06a
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    • pp.502-504
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    • 2008
  • A new output inductor less phase shift full bridge converter with current reduction technique for server power application is proposed in this paper. The proposed converter can reduce the current stress by using the auxiliary circuit. Since the auxiliary circuit causes the additional resonance between the leakage inductor and auxiliary capacitor before the powering period, the proposed converter has lower current stress even no output filter inductor. Small size and circulating energy can be also the merits of the proposed converter. The operational principles and analysis are presented. Experimental results demonstrate that the current stress can be reduced effectively by using the auxiliary circuit without large output filter inductor.

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The Effect of Deformation Stress-strain and Temperature on the $I_c$ Degradation of Bi-2223/Ag Tapes

  • Ha, Hong-Soo;Kim, Sang-Cheol;Ha, Dong-Woo;Oh, Sang-Soo;Joo, Jin-Ho
    • Proceedings of the Korean Powder Metallurgy Institute Conference
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    • 2006.09b
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    • pp.1251-1252
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    • 2006
  • In order to investigate 95% retained critical current of Bi-2223/Ag tapes under various stress-strain conditions, load cell attached tension and bending apparatus was used. The critical current of stress-strained tape was degraded below 95% retained critical current when tension and bending was simultaneously applied together. But only one of this tension or bending did not degrade the tape below 95% retained critical current. Deformation temperature was important to maintain the 95% retained Ic of Bi-2223/Ag tapes after bending or tension deformation because mechanical strength of tapes can be changed drastically between room temperature and 77 K.

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Hot-Carrier Induced GIDL Characteristics of PMOSFETs under DC and Dynamic Stress (직류 및 교류스트레스 조건에서 발생된 Hot-Carrier가 PMOSFET의 누설전류에 미치는 영향)

  • 류동렬;이상돈;박종태;김봉렬
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.12
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    • pp.77-87
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    • 1993
  • PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

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Experimental Study for Gate Trap and Generation Current using DCIV Method

  • Kim, Young Kwon;Lee, Dong Bin;Choi, Won Hyeok;Park, Taesik;Lee, Myoung Jin
    • KEPCO Journal on Electric Power and Energy
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    • v.2 no.2
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    • pp.223-225
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    • 2016
  • The newly proposed analysis method using a direct-current current-voltage (DCIV) simulation is introduced for investigating leakage current composing MOS transistor. From comparing the density and location of traps using DCIV method and investigating the leakage current of gate channel transistor, we proposed the graphical analysis method to correlate the DCIV current and leakage mechanism by the traps. And, our graphical method intuitively explains that leakage current in MOS transistor is well correlated with the DCIV current of the MOS transistor arrays due to two kinds of traps created by Fowler-Nordheim (F-N) stress and Hot carrier stress, respectively.

New Zero-Current-Transition (ZCT) Circuit Cell Without Additional Current Stress

  • Kim, C.E.;Park, E.S.;G.W. Moon
    • Journal of Power Electronics
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    • v.3 no.4
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    • pp.215-223
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    • 2003
  • In this paper, a new zero-current-transition (ZCT) circuit cell is proposed. The main switch is turned-off under the zero current and zero voltage condition, and there is no additional current stress and voltage stress in the main switch and the main diode, respectively. The auxiliary switch is turned-off under the zero voltage condition, and the main diode is turned-on under the zero voltage condition. The resonant current required to obtain the ZCT condition is relatively small and regenerated to the input voltage source. The operational principles of a boost converter integrated with the proposed ZCT circuit cell are analyzed and verified by the simulation and experimental results.

The Study on the Trap Density in Thin Silicon Oxide Films

  • Kang, C.S.;Kim, D.J.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.04b
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    • pp.43-46
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    • 2000
  • In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

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Analysis of bridging Stress Effect of Polycrystlline Aluminas Using Double Cantilever Beam Method (Double Cantilever Beam 방법을 이용한 다결정 알루미나의 Bridging 응력효과 해석 III. 다결정 알루미나의 Bridging 응력분포)

  • 손기선;이성학;백성기
    • Journal of the Korean Ceramic Society
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    • v.33 no.5
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    • pp.602-615
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    • 1996
  • The purpose of the present study is to investigate the microstructural effect on the R-curve behavior in three aluminas with different grain size distributions by analyzing the bridging stress distribution. The crack opening displacement (COD) according to the distance behind the stationary crack tip was measured using an in situ SEM fracture method. The measured COD values in the fine-grained alumina agreed well with Wiederhorn's sollution while they deviated from Wiederhorn's solution in the two coarse-grained aluminas because of the increase of the crack closure due to the grain interface bridging in the crack wake. A numerical fitting procedure was conducted by the introduction of the power-law relation and the current theoretical model together with the measured COD's in order to obtain the bridging stress distribution. The results indicated that the bridging stress function and the R-curve computed by the current model were consistent with those computed by the power-law relation providing a reliable evidence for the bridging stress analysis of the current model. The strain-softening exponent in the power-law relation n, was calculated to be in the range from 2 to 3 and was closely related to the grain size distribution. Thus it was concluded from the current theoretical model that the grain size distribution affected greatly the bridging stress distribution thereby resulting in the quantitative analysis of microfracture of polycrystalline aluminas through correlating the local-fracture-cont-rolling microstructure.

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Influences of Electrodeposition Variables on Mechanical Properties of Ni-Mn Electrodepositions (Ni-Mn 전착층의 기계적 성질에 미치는 공정조건의 영향)

  • Shin, Ji-Wung;Yang, Seung-Gi;Hwang, Woon-Suk
    • Corrosion Science and Technology
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    • v.13 no.3
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    • pp.102-106
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    • 2014
  • Nickel electrodeposition from sulfamate bath has several benefits such as low internal stress, high current density and good ductility. In nickel deposited layers, sulfur induces high temperature embrittlement, as Ni-S compound has a low melting temperature. To overcome high temperature embrittlement problem, adding manganese is one of the good methods. Manganese makes Mn-S compound having a high melting temperature above $1500^{\circ}C$. In this work, the mechanical properties of Ni-Mn deposited layers were investigated by using various process variables such as concentration of Mn$(NH_2SO_3)_2$, current density, and bath temperature. As the Mn content of electrodeposited layers was increased, internal stress and hardness were increased. By increasing current density, internal stress increased, but hardness decreased. With increasing the bath temperature from 55 to $70^{\circ}C$, internal stress of Ni deposit layers decreased, but hardness didn't change by bath temperature. It was likely that eutectoid manganese led to lattice deformation, and the lattice deformation increased hardness and internal stress in Ni-Mn layers. Increasing current density and decreasing bath temperature would increase a mount of $H_2$ absorption, which was a cause for the rise of internal stress.

The Work Stress and Coping Type of Nurses in Hospital (병원 간호사의 직무스트레스와 대처유형)

  • Lee, Young-Mee
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.11
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    • pp.230-235
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    • 2016
  • The purpose of this study was to investigate the stress from work and stress coping methods of hospital nurses. The study design was a descriptive survey research. There were a total of 168 hospital nurses included in this study. Data were analyzed by t test, ANOVA (Sheffe's test), and Pearson's correlation coefficient using SPSS/WIN17.0. The stress level from work was 4.27 and stress coping methods was 2.67. Marital status was positively correlated with education level, current department, career duration, and current position. The education level was positively correlated with career period and current position. Current position was positively correlated with stress coping methods. A further follow-up study on nurses in hospital is necessary to relieve stress from work and to increase better stress coping methods. Moreover, to decrease the stress from work of nurses, it is necessary to develop a program that helps them to cope with stress. In addition, these findings contribute to the development of such program.

Hot-Carrier-Induced Degradation in Submicron MOS Transistors (Submicron MOS 트랜지스터의 뜨거운 운반자에 의한 노쇠현상)

  • 최병진;강광남
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.7
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    • pp.780-790
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    • 1988
  • We have studied the hot-carrier-induced degradation caused by the high channel electric field due to the decrease of the gate length of MOSFET used in VLSI. Under DC stress, the condition in which maximum substrate current occures gave the worst degradation. Under AC dynamic stress, other conditions, the pulse shape and the falling rate, gave enormous effects on the degradation phenomena, especially at 77K. Threshold voltage, transconductance, channel conductance and gate current were measured and compared under various stress conditions. The threshold voltage was almost completely recovered by hot-injection stress as a reverse-stress. But, the transconductance was rapidly degraded under hot-hole injection and recovered by sequential hot-electron stress. The Si-SiO2 interface state density was analyzed by a charge pumping technique and the charge pumping current showed the same trend as the threshold voltage shift in degradation process.

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