• 한국전기전자재료학회논문지
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• 제29권10호
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• pp.595-600
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• 2016

In this paper, the oxide currents of thin silicon oxides is investigated. The oxide currents associated with the on time of applied voltage were used to measure the distribution of voltage stress induced traps in thin silicon oxide films. The stress induced leakage currents were due to the charging and discharging of traps generated by stress voltage in the silicon oxides. The stress induced leakage current will affect data retention in memory devices. The oxide current for the thickness dependence of stress current and stress induced leakage currents has been measured in oxides with thicknesses between $109{\AA}$, $190{\AA}$, $387{\AA}$, and $818{\AA}$ which have the gate area $10^{-3}cm^2$. The oxide currents will affect data retention and the stress current, stress induced leakage current is used to estimate to fundamental limitations on oxide thicknesses.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Transactions on Electrical and Electronic Materials
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• 제4권6호
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.855-858
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• 2001

The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.209-212
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• 2004

In this paper, The stress induced leakage currents of thin silicon oxides is investigated in the nano scale structure implementation for Soc. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41\square\;and\;113.4\square,$ which have the channel width x length 10x1um, respectively. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1997년도 추계학술대회 논문집
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• pp.102-105
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• 1997

The thickness dependence of stress voltage oxide currents has been measured in oxides with thicknesses between 10nm and 80nm. The oxide currents were shown to be composed of stress current and transient current. The stress current was caused by trap assited tunneling through the oxide. The transient current was caused by the tunneling charging and discharging of the trap in the interfaces. The stress current was used to estimate to the limitations on oxide thicknesses. The transient current was used to the data retention in memory devices.

• 한국결정성장학회지
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• 제8권3호
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• pp.411-418
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• 1998

LPCVD 방법으로 실리콘 산화막 두께 10nm에서 80nm인 MOS를 제작하였다. 그리고 스트레스 전계 산화막 전류의 두께 의존성을 조사하였다. 산화막 전류는 스트레스 전류와 전이전류로 구성되어 있음을 보여 주었다. 스트레스 전류는 스트레스 유기 누설전류와 직류전류로 이루어졌으며 산화막을 통하는 트립 어시스트 터널링으로 행해진다. 전이전류는 계면에서 트랩의 터널링 충전과 방전에 의해 이루어진다. 스트레스 전류는 산화막 전류의 두계 한계를 평가하는데 이용되고 전이전류는 기억소자에서 데이터 유지에 사용된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.371-371
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• 2010

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the MEMS implementation with nano structure. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $41{\AA}$, which have the gate area $10^{-3}cm^2$. The stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• 동서간호학연구지
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• 제12권1호
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• pp.43-55
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• 2006

Purpose: This study was a descriptive study to assess the relationships between acculturative stress and current perception of stress in Korean immigrants. Methods: The subjects consisted of 154 community-dwelling Korean immigrant living in the USA. Data collection was conducted through the use of questionnaires. The instruments for this study were Acculturative stress (12 items), The Global Assessment of Recent Scale(8 items). The collected data were analysed using SPSS PC 12.0 Programme for Frequency, Percentage, t-test, ANOVA, Duncan test and Pearson's correlation coefficient according to the purpose of this study. Results: 1) The average item score for acculturative stress was 17.17. The average item score for current perception of stress was 26.56. 2) Acculturative stress was positively related to current perception of stress (r=.360, p<.01). 3) Acculturative stress was significantly different according to educational level (F=2.709, p=.047), occupation (F=16.202, p=.000), perceived income comfort level (F=26.666, p=.000), and type of residence (F=2.672, p=.050). The Current perception of stress was significantly different according to age (F=7.380, p=.000), marital status (F=5.354, p=.006), perceived income comfort level (F=12.738, p=.000), and type of residence(F=4.207, p=.007). Conclusion: Theses findings help to clarify relationships between acculturative stress and current perception of stress in Korean immigrants. Therefore, the result of study provide clues for the quality of life of Korean immigrants.

• 대한전자공학회논문지TE
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• 제39권4호
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• pp.335-340
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• 2002

본 논문에서 얇은 실리콘 산화막의 스트레스 유기 누설전류는 나노 구조를 갖는 트랜지스터의 ULSI 실현을 위하여 조사하였다. 인가전압의 온 오프 시간에 따른 스트레스전류와 전이전류는 실리콘 산화막에 고전압 스트레스 유기 트랩분포를 측정하기 위하여 사용하였다. 스트레스전류와 전이전류는 고스트레스 전압에 의해 발생된 트랩의 충방전과 양계면 가까이에 발생된 트랩의 터널링에 기인한다. 스트레스 유기 누설전류는 전기적으로 기록 및 소거를 실행하는 메모리 소자에서 데이터 유지 능력에 영향이 있음을 알았다. 스트레스전류, 전이전류 그리고 스트레스 유기 누설전류의 두께 의존성에 따른 산화막 전류는 게이트 면적이 10/sup －3/㎠인 113.4Å에서 814Å까지의 산화막 두께를 갖는 소자에서 측정하였다. 스트레스 유기 누설전류, 스트레스전류, 그리고 전이전류는 데이터 유지를 위한 산화막 두께의 한계에 대해 연구 조사하였다.