• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.181-190
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• 2019

Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.4
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• pp.391-396
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• 2009

In this paper, a control algorithm for DC-Link voltage unbalancing compensation of a four-switch inverter for a three-phase BLDC motor drive is proposed. Compared with a conventional six-switch inverter, the split source of the four-switch inverter can be obtained by splitting DC-link capacitor into two capacitors to drive the three phase BLDC motor. The voltages across each of two capacitors are not always equal in steady state because of the unbalance in the impedance of the DC-link capacitors $C_1$ and $C_2$ or the variable current flowed into the capacitor's neutral point in motor control. Despite the unbalance, if the BLDC motor may be run for a long time the voltage across one of the capacitors is more increased. So the unbalance in the capacitors voltages will be accelerated. As a result, The current ripple and torque ripple is increased due to the fluctuation of input current which flows into 3-phase BLDC motor. According to that, the vibration of motor will be increased and the whole system will be instable. This paper presents a control algorithm for DC-Link voltage unbalancing compensation. The sampling from the voltages across each of two capacitors is used to perform the voltage control of DC-Link by using the feedforward controller.

• Journal of Advanced Navigation Technology
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• v.23 no.1
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• pp.69-76
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• 2019

In this paper, a design method for an enhanced-sensitivity microwave sensor based on microstrip defected ground structure was studied for the permittivity measurement of planar dielectric substrates. The proposed sensor was designed by modifying the ridge structure of an H-shaped aperture into the shape of a capacitor symbol. The sensitivity of the proposed sensor was compared with that of a conventional sensor based on a double-ring complementary split ring resonator(DR-CSRR). Two sensors were designed and fabricated on a 0.76-mm-thick RF-35 substrate so that the transmission coefficient would resonate at 1.5 GHz in the absence of the substrate under test. Five types of taconic substrates with a relative permittivity ranging from 2.17 to 10.2 were selected asthe substrate under test. Experiment results show that the sensitivity of the proposed sensor, which is measured by the shift in the resonant frequency of the transmission coefficient, is 1.31 to 1.62 times higher than that of the conventional DR-CSRR-based sensor.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1190-1199
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• 2015

This paper presents a new resonant converter to achieve the soft switching of power devices. Two full-bridge converters are connected in series to clamp the voltage stress of power switches at V_in/2. Thus, power MOSFETs with a 500V voltage rating can be used for 800V input voltage applications. Two flying capacitors are connected on the AC side of the two full-bridge converters to automatically balance the two split input capacitor voltages in every switching cycle. Two resonant tanks are used in the proposed converter to share the load current and to reduce the current stress of the passive and active components. If the switching frequency is less than the series resonant frequency of the resonant tanks, the power MOSFETs can be turned on under zero voltage switching, and the rectifier diodes can be turned off under zero current switching. The switching losses on the power MOSFETs are reduced and the reverse recovery loss is improved. Experiments with a 1.5kW prototype are provided to demonstrate the performance of the proposed converter.

• 전기의세계
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• v.17 no.3
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• pp.29-38
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• 1968

The development of the frequency converter using semiconductor enables to easily control the speed of A.C. motors. It is now technically possible and economically feasible to provide them with power at variable frequency, using silicon-controlled-rectifier (or thyristor) inverters. In such a case, if an induction motor is to be operated efficiently over a wide speed range, it must be supplied from a variable-frequency source whose frequency is adjustable over a range similar to that required for the motor speed. It is desired to observe how several characteristics are changed such as primary current, torque-speed, etc. Although the characteristics could be obtained by means of the conventional method, it requires very complicated calculation. It is assumed that the charateristics above are easily investigated by means of current diagram method from variable circuit constants relating to the motor which is designed in rated frequency. In this paper, the results of the study on the current-diagram method and its application are described as follows; (1) In order to discuss the construction of current diagram, the equation of the stator current with adjustable frequency was derived for applying the Current Diagram Method. (2) The radius, the center of the current circle and current vector locus at any desired frequency could be easily determined with the aid of both above mentioned equation and the standard current diagram at reference frequency. (3) This method could be applicable to the various types of Induction Motors, and this paper has dealt with its application to the capacitor, split-phase and 2-phase types of motors.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.99-99
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• 2013

In this talk, I will present two research works in progress, which are: i) mapping of piezoelectric polarization and associated charge density distribution in the heteroepitaxial InGaN/GaN multi-quantum well (MQW) structure of a light emitting diode (LED) by using inline electron holography and ii) in-situ observation of the polarization switching process of an ferroelectric Pb(Zr1-x,Tix)O3 (PZT) thin film capacitor under an applied electric field in transmission electron microscope (TEM). In the first part, I will show that strain as well as total charge density distributions can be mapped quantitatively across all the functional layers constituting a LED, including n-type GaN, InGaN/GaN MQWs, and p-type GaN with sub-nm spatial resolution (~0.8 nm) by using inline electron holography. The experimentally obtained strain maps were verified by comparison with finite element method simulations and confirmed that not only InGaN QWs (2.5 nm in thickness) but also GaN QBs (10 nm in thickness) in the MQW structure are strained complementary to accommodate the lattice misfit strain. Because of this complementary strain of GaN QBs, the strain gradient and also (piezoelectric) polarization gradient across the MQW changes more steeply than expected, resulting in more polarization charge density at the MQW interfaces than the typically expected value from the spontaneous polarization mismatch alone. By quantitative and comparative analysis of the total charge density map with the polarization charge map, we can clarify what extent of the polarization charges are compensated by the electrons supplied from the n-doped GaN QBs. Comparison with the simulated energy band diagrams with various screening parameters show that only 60% of the net polarization charges are compensated by the electrons from the GaN QBs, which results in the internal field of ~2.0 MV cm-1 across each pair of GaN/InGaN of the MQW structure. In the second part of my talk, I will present in-situ observations of the polarization switching process of a planar Ni/PZT/SrRuO3 capacitor using TEM. We observed the preferential, but asymmetric, nucleation and forward growth of switched c-domains at the PZT/electrode interfaces arising from the built-in electric field beneath each interface. The subsequent sideways growth was inhibited by the depolarization field due to the imperfect charge compensation at the counter electrode and preexisting a-domain walls, leading to asymmetric switching. It was found that the preexisting a-domains split into fine a- and c-domains constituting a $90^{\circ}$ stripe domain pattern during the $180^{\circ}$ polarization switching process, revealing that these domains also actively participated in the out-of-plane polarization switching. The real-time observations uncovered the origin of the switching asymmetry and further clarified the importance of charged domain walls and the interfaces with electrodes in the ferroelectric switching processes.