• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.803-812
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• 2006

This paper analytically evaluates the FEC(Forward Error Correction) symbol size's effect on the performance and energy consumption of 802.11 protocol with the block FEC algorithm over WSN(Wireless Sensor Network). Since the basic recovery unit of block FEC algorithms is symbols not bits, the FEC symbol size affects the packet correction rate even with the same amount of FEC check bits over a given WSN channel. Precisely, when the same amount of FEC check bits are allocated, the small-size symbols are effective over channels with frequent short bursts of propagation errors while the large ones are good at remedying the long rare bursts. To estimate the effect of the FEC symbol site, the paper at first models the WSN channel with Gilbert model based on real packet traces collected over TIP50CM sensor nodes and measures the energy consumed for encoding and decoding the RS (Reed-Solomon) code with various symbol sizes. Based on the WSN channel model and each RS code's energy expenditure, it analytically calculates the transmission efficiency and power consumption of 802.11 equipped with RS code. The computational analysis combined with real experimental data shows that the RS symbol size makes a difference of up to 4.2% in the transmission efficiency and 35% in energy consumption even with the same amount of FEC check bits.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.1
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• pp.66-75
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• 2000

In this paper, we present the efficient image transmission system using designed source-channel combined coder in W-CDMA mobile communication system. In proposed schemes, we decompose the wavelet transformed hierarchical band-images into some types of different size blocks which have different properties in error sensitivity. The RS(Reed-Solomon) coder with different coding rate is used for each decomposed source blocks which has different importance. In addition, we combine retransmitted error frames in Truncated Hybrid Type I ARQ. The proposed algorithm shows efficient image transmission methods because it is not much degraded in PSNR compared with the existing not combined source-channel coder in erroneous wireless channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.848-854
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• 2009

DVB-SSP is a new broadcasting system for hybrid satellite communications, which supports mobile handhold systems and fixed terrestrial systems. An upper layer, including erasure Reed-Solomon error correction combined with cyclic redundancy check. However, a critical factor must be considered in upper layer decoding. If there is only one bit error in an IP packet, the entire IP packet is considered as unreliable bytes, even if it contains correct bytes. If, for example, there is one real byte error, in an If packet of 512 bytes, 511 correct bytes are erased from the frame. Therefore, this paper proposed upper layer decoding methods; hybrid decoding. By means of simulation we show that the performance of the proposed decoding algorithm is superior to that of the conventional one in AWGN channel and TI channel.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.76-81
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• 2006

Recently, Finite field is applied the cryptography in the modern multimedia communication. Especially, block codes such as Elliptic Curve Cryptosystem and Reed-Solomon code among the error correcting codes are defined with finite field. Also, finite field algorithm is conducting the research actively because many kind of application parts need the real time operating ability therefore the exclusive hardware have been implementing. In this paper, we proposed the inverse finite field algorithm over GF($2^8$) using finite composite field and implemented in a hardware, and then compare this hardware with the currently used 'Itoh and Tsujii' hardware in respect to structure, area and computation time. Furthermore, this hardware was inserted into the AES SubBytes block and implemented on FPGA emulator board to confirm that the superiority of the proposed algorithm through the performance evaluation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.175-183
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• 2006

This letter proposes a Direct Sequence Spread Spectrum (DS-SS)-based Flight Termination System(FTS) and show the simulation results and implements the system using FRGAs. The DS-SS FTS has immunity interference signals and the influence of jamming signal. Moreover, a DS-SS FTS can provides effects on an authentication and encryption with spread codes. And the system uses more less power than an analog FM system. We used Reed-Solomon (32, 28) code and triple Data Encryption Standard(3DES) for error correction and data encryption. Also we used counter algorithm for unauthenticated device's attack The spread codes of In-phase channel and Quadrature channel were generated by Gold sequence generators. The system was implemented in Altera APEX20K100E FPGA for the ground system and EPF10K100ARC240-3 for the airborne system.