• KIISE Transactions on Computing Practices
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• v.22 no.2
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• pp.95-100
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• 2016

In the current era of big data and cloud computing, the amount of data utilized is increasing, and various systems to process this big data rapidly are being developed. A distributed file system is often used to store the data, and glusterFS is one of popular distributed file systems. As computer technology has advanced, NAND flash SSDs (Solid State Drives), which are high performance storage devices, have become cheaper. For this reason, datacenter operators attempt to use SSDs in their systems. They also try to install glusterFS on SSDs. However, since the glusterFS is designed to use HDDs (Hard Disk Drives), when SSDs are used instead of HDDs, the performance is degraded due to structural problems. The problems include the use of I/O-cache, Read-ahead, and Write-behind Translators. By removing these features that do not fit SSDs which are advantageous for random I/O, we have achieved performance improvements, by up to 255% in the case of 4KB random reads, and by up to 50% in the case of 64KB random reads.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.1
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• pp.1-7
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• 2012

In this paper, An X-band solid state power amplifier(SSPA) for pulse compressed microwave signal with 60Watt power and power added efficiency(PAE) above 30% is described. Designed 60Watt high power amplifier(HPA) was implemented by cascade coupled amplifiers, and it is consisted on three stage drive amplifiers with internally matched GaAs FET and one stage main power amplifier with an internally matched GaN HEMT. The designed SSPA has performance with more than total power gain 37dB and output power 48dBm(60-W) in condition of frequency range $9.41{\pm}0.03GHz$, pulse period width under 1ms and duty cycle under 10%. The implemented SSPA can apply to high quality digital marine radar applications with pulse compression technique.

• Journal of the Korea Institute of Military Science and Technology
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• v.26 no.3
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• pp.227-233
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• 2023

In this paper, to substitute the existing TWTA(Travailing Wave Tube Amplifier) component in small radar system, we developed the Ku band SSPA(Solid-State Power Amplifier) based on the fabrication of power MMIC (Monolithic Microwave Integrated Circuit) chips. For the development of the 500 W SSPA, the 40 W-grade power MMIC was designed by ADS(Advanced Design System) at Keysight company with UMS GH015 library, and was processed by UMS foundry service. And 70 W main power modules were achieved the 2-way T-junction combiner method by using the 40 W-grade power MMICs. Finally, the 500 W SSPA was fabricated by the wave guide type power divider between the drive power amplifier and power modules, and power combiner with same type between power modules and output port. The electrical properties of this SSPA had 504 W output power, -58.11 dBc spurious, 1.74 °/us phase variation, and -143 dBm/Hz noise level.

• The Journal of the Korea Contents Association
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• v.16 no.10
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• pp.477-482
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• 2016

This paper presents a new method of parity storing for ECC(error correcting code) in SSD (solid-state drive) and suitable structure of the controller. In general usage of NAND flash memory, we partition a page into data and spare area. ECC parity is stored in the spare area. The method has overhead on area and timing due to access of the page memory discontinuously. This paper proposes a new parity policy storing method that reduces overhead and R(read)/W(write) timing by using whole page area continuously without partitioning. We analyzed overhead and R/W timing. As a result, the proposed parity storing has 13.6% less read access time than the conventional parity policy with 16KB page size. For 4GB video file transfer, it has about a minute less than the conventional parity policy. It will enhance the system performance because the read operation is key function in SSD.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.143-151
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• 2013

NAND flash-based SSDs (Solid State Drive) have advantages of fast input/output performance and low power consumption so that they could be widely used as storages on tablet, desktop PC, smart-phone, and server. But, SSD has the disadvantage of wear-leveling due to increase of the number of writes. In order to improve the lifespan of the SSD, a variety of data deduplication techniques have been introduced. General fixed-size splitting method allocates fixed size of chunk without considering locality of data so that it may execute unnecessary chunking and hash key generation, and variable-size splitting method occurs excessive operation since it compares data byte-by-byte for deduplication. This paper proposes adaptive chunking method based on application locality and file name locality of written data in SSD-based server storage. The proposed method split data into 4KB or 64KB chunks adaptively according to application locality and file name locality of duplicated data so that it can reduce the overhead of chunking and hash key generation and prevent duplicated data writing. The experimental results show that the proposed method can enhance write performance, reduce power consumption and operation time compared to existing variable-size splitting method and fixed size splitting method using 4KB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.48-56
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• 2011

Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.

• Journal of KIISE
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• v.42 no.6
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• pp.691-698
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• 2015

Application launch time is an important performance metric to user experience in desktop and laptop environment, which mostly depends on the performance of secondary storage. Application launch times can be reduced by utilizing solid-state drive (SSD) instead of hard disk drive (HDD). However, considering a cost-performance trade-off, utilizing SSDs as caches for slow HDDs is a practicable alternative in reducing the application launch times. We propose a new SSD caching scheme which migrates data blocks from HDDs to SSDs. Our scheme operates entirely in the file system level and does not require an extra layer for mapping SSD-cached data that is essential in most other schemes. In particular, our scheme does not incur mapping overheads that cause significant burdens on the main memory, CPU, and SSD space for mapping table. Experimental results conducted with 8 popular applications demonstrate our scheme yields 56% of performance gain in application launch, when data blocks along with metadata are migrated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.291-302
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• 2013

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.12
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• pp.1083-1090
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• 2015

We designed and manufactured Ka-band SSPA include drive amplifier and high power amplifier MMICs by $0.15{\mu}m$ GaN commercial process. Also, we fabricated main components micro-strip line to WR28 waveguide transition and WR28 wave guide power combiner for Ka-band SSPA. This Ka-band SSPA shows saturated output power 44.2 dBm, power added efficiency 16.6 % and power gain 39.2 dB at 29~31 GHz frequency band.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.4
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• pp.85-91
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• 2019

In this paper, we propose a new logging and recovery scheme that is suited for the high-performance transaction processing system base on flash memory storage. The proposed scheme is designed by considering flash's I/O characteristic of asymmetric costs between page update/read operations. That is, we substitute the costly update operation with writing and real-time usage of snapshot log, which is for the page-level physical redo. From this, we can avoid costly rewriting of a dirty page when it is evicted form a buffering pool. while supporting efficient revery procedure. The proposed scheme would be not lucrative in the case of HDD-based system. However, the proposed scheme offers the performance advance sush as a reduced number of updates and the fast system recovery time, in the case of flash storage such as SSD (solid state drive). Because the proposed scheme can easily be applied to existing systems by saving our snapshot records and ordinary log records together, our scheme can be used for improving the performance of upcoming SSD-based database systems through a tiny modification to existing REDO algorithms.