• Korean Journal of Materials Research
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• v.8 no.8
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• pp.744-750
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• 1998

Unlike common device, MEMS(micro-electro-mechanical system) device consists of very small mechanical structures which determine the performance of the device. Because of its small mechanical structure inside. MEMS device is very sensitive to thermal stress caused by CTE(coefficient of thermal expansion) mismatch between its components. Therefore, its characteristics are affected by material properties. process temperature. and dimensions of each layer such as chip, adhesive and substrate. In this study. we investigated the change of the thermal stress in the chip attached to a substrate. With computer-aided finite element method (FEM), the computer simulation of the thermal stress was conducted on variables such as bonding material, process temperature, bonding layer thickness and die size. The commercial simulation program, ABAQUS ver5.6, was used. Subsequently 3-layer test samples were fabricated, and their degree of bending were measured by 3-D coordinate measuring machine. The experimental results were in good agreement with the simulation results. This study shows that the bonding layer could be the source of stress or act as the buffer layer for stress according to its elastic modulus and CTE. Solder adhesive layer was the source of stress due to its high elastic modulus, therefore high compressive stress was developed in the chip. And the maximum tensile stress was developed in the adhesive layer. On the other hand, polymer adhesive layer with low elastic modulus acted as buffer layer, and resulted in lower compressive stress. The maximum tensile stress was developed in the substrate.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.25.1-25.1
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• 2011

Over the past few decades, metallic nanoparticles (NPs) have been of great interest due to their unique mesoscopic properties which distinguish them from those of bulk metals; such as lowered melting points, greater versatility that allows for more ease of processability, and tunable optical and mechanical properties. Due to these unique properties, potential opportunities are seen for applications that incorporate nanomaterials into optical and electronic devices. Specifically, the development of metallic NPs has gained significant interest within the electronics field and technological community as a whole. In this study, gold (Au) pads for surface finish in electronic package were developed by inkjet printing of Au NPs. The microstructures of inkjet-printed Au film were investigated by various thermal treatment conditions. The film showed the grain growth as well as bonding between NPs. The film became denser with pore elimination when NPs were sintered under gas flows of $N_2$-bubbled through formic acid ($FA/N_2$) and $N_2$, which resulted in improvement of electrical conductance. The resistivity of film was 4.79 ${\mu}{\Omega}$-cm, about twice of bulk value. From organic anlayses of FTIR, Raman spectroscopy, and TGA, the amount of organic residue in the film was 0.43% which meant considerable removal of the solvent or organic capping molecules. The solder ball shear test was adopted for solderability and shear strength value was 820 gf (1 gf=9.81 mN) on average. This shear strength is good enough to substitute the inkjet-printed Au nanoparticulate film for electroplating in electronic package.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.4
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• pp.237-240
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• 2016

The improvement of irradiation intensity and irradiation uniformity is essential for large area and high power UVA light source application. In this study, large number of chips bonded by micro soldering technique were driven by low current, and current limiting diodes were configured to supply constant current to parallel circuits consisting of large number of series strings. The dimension of light source module circuit board was $350{\times}90mm^2$ and 16,650 numbers of 385 nm flip chip LEDs were used with a configuration of 90 parallel and 185 series strings. The space between LEDs in parallel and series strings were maintained at 1.9 mm and 1.0 mm distance, respectively. The size of the flip chip was $750{\times}750{\mu}m^2$ were used with contact pads of $260{\times}669{\mu}m^2$ size, and SAC (96.5 Sn/3.0 Ag/0.5 Cu) solder was used for flip chip bonding. The fabricated light source module with 7.5 m A supply current showed temperature rise of $66^{\circ}C$, whereas irradiation was measured to be $300mW/cm^2$. Inaddition, 0.23% variation of the constant current in each series string was demonstrated.

• Proceedings of the KWS Conference
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• 2009.11a
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• pp.217-220
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• 2009

Conductive adhesives have been investigated for use in microelectronics packaging as a lead-free solder substitute due to their advantages, such as low bonding temperature. However, high resistivity and poor mechanical behavior may be the limiting factors for the development of conductive adhesives. The metal fillers and the polymer resins provide electrical and mechanical interconnections between surface mount device components and a substrate. As metal fillers used in conductive adhesives, silver is the most commonly used due to its high conductivity and the stability. However the cost of conductive adhesives with silver fillers is much higher than usual lead-free solders and silver has poor electro-migration performance. So, copper can be a promising candidate for conductive filler metal due to its low resistivity and low cost, but oxidation causes this metal to lose its conductivity. In this study, electrically conductive adhesives (ECAs) using surface modified copper fillers were developed. Especially, in order to overcome the problem associated with the oxidation of copper, copper particles were coated with silver, and the silver-coated copper was tested as a filler metal. Especially the effect of silver coating on the electrical resistance just after curing and after aging was investigated. As a result, it was found that the electrical resistance of ECA with silver-coated copper filler was clearly lower and more stable than that of ECA with pure copper filler after curing process. And, during high temperature storage test, the degradation rate of electrical resistance for ECA with silver coated copper filler was quite slower than that for ECA with pure copper filler.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.1
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• pp.1-16
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• 2023

Recently, the shift to next-generation wide-bandgap (WBG) power semiconductor for electric vehicle is accelerated due to the need to improve power conversion efficiency and to overcome the limitation of conventional Si power semiconductor. With the adoption of WBG semiconductor, it is also required that the packaging materials for power modules have high temperature durability. As an alternative to conventional high-temperature Pb-based solder, Ag sintering die attach, which is one of the power module packaging process, is receiving attention. In this study, we will introduce the recent research trends on the Ag sintering die attach process. The effects of sintering parameters on the bonding properties and methodology on the exact physical properties of Ag sintered layer by the realization 3D image are discussed. In addition, trends in thermal shock and power cycle reliability test results for power module are discussed.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.59-64
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• 2013

In-situ annealing tests of Cu/Ni/Au/Sn-Ag/Cu micro-bump for 3D IC package were performed in an scanning electron microscope chamber at $135-170^{\circ}C$ in order to investigate the growth kinetics of intermetallic compound (IMC). The IMC growth behaviors of both $Cu_3Sn$ and $(Cu,Ni,Au)_6Sn_5$ follow linear relationship with the square root of the annealing time, which could be understood by the dominant diffusion mechanism. Two IMC phases with slightly different compositions, that is, $(Cu,Au^a)_6Sn_5$ and $(Cu,Au^b)_6Sn_5$ formed at Cu/solder interface after bonding and grew with increased annealing time. By the way, $Cu_3Sn$ and $(Cu,Au^b)_6Sn_5$ phases formed at the interfaces between $(Cu,Ni,Au)_6Sn_5$ and Ni/Sn, respectively, and both grew with increased annealing time. The activation energies for $Cu_3Sn$ and $(Cu,Ni,Au)_6Sn_5$ IMC growths during annealing were 0.69 and 0.84 eV, respectively, where Ni layer seems to serve as diffusion barrier for extensive Cu-Sn IMC formation which is expected to contribute to the improvement of electrical reliability of micro-bump.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2013.04a
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• pp.835-841
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• 2013

Modern solid-state gyroscopes (HRG) with hemispherical resonators from high-purity quartz glass and special surface superfinishing and ultrathin gold coating become the best instruments for precise-grade inertial reference units (IRU) targeting long-term space missions. Designing of these sensors could be a notable contribution into development of Korea as a space nation. In participial, 40mm diameter thin-shell resonator from high-purity fused quartz, fabricated as a single-piece with its supporting stem has been designed, machined, etched, tuned, tested, and delivered by STM Co. (ATS of Ukraine) several years ago; an extremely-high Q-factor (upto 10~20 millions) has been shown. Understanding of the best way how to match such a unique sensor with inner glass assembly of the gyro means how to use the high potential in a maximal extent; and this has become the urgent task. Inner quartz glass assembly has a very thin indium (In) layer soldered the resonator and its silica base (case), but effects of internal resonances between operational modal pair of the shell-cup and its side (parasitic) modes can notable degrade the potential of the sensor as a whole, instead of so low level of resonator's intrinsic losses. Unfortunately, there are special combinations of dimensions of the parts (so-called, "resonant sizes"), when intensive losses of energy occurs. The authors proposed to use the length of stem's fixture as an additional design parameter to avoid such cases. So-called, a cyclic scheme of finite element method (FEM) and ANSYS software were employed to estimate different combinations of gyro assembly parameters. This variant has no mismatches of numerical origin due to FEM's discrete mesh. The optimum length and dangerous "resonant lengths" have been found. The special attention has been paid to analyses of 3D effects in a cup-stem transient zone, including determination of a difference between the positions of geometrical Pole of the resonant hemisphere and of its "dynamical Pole", i.e., its real zone of oscillation node. Boundary effects between the shell (cup) and 3D short "beams" (inner and outer stems) have been ranged. The results of the numerical experiments have been compared with the classic model of a quasi-hemispherical shell band with inextensional midsurface, and the solution using Rayleigh's functions of the $1^{st}$ and $2^{nd}$ kinds. To guarantee the truth of the recommended sizes to a designer of the real device, the analytical and FEM results have been compared with experimental data for a party of real resonators. The consistency of the results obtained by different means has been shown with errors less than 5%. The results notably differ from the data published earlier by different researchers.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.