• Title/Summary/Keyword: Solder Bonding

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DRAM Package Substrate Using Via Cutting Structure (비아 절단 구조를 사용한 DRAM 패키지 기판)

  • Kim, Moon-Jung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.7
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    • pp.76-81
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    • 2011
  • A new via cutting structure in 2-layer DRAM package substrate has been fabricated to lower its power distribution network(PDN) impedance. In new structure, part of the via is cut off vertically and its remaining part is designed to connect directly with the bonding pad on the package substrate. These via structure and substrate design not only provide high routing density but also improve the PDN impedance by shortening effectively the path from bonding pad to VSSQ plane. An additional process is not necessary to fabricate the via cutting structure because its structure is completed at the same time during a process of window area formation. Also, burr occurrence is minimized by filling the via-hole inside with a solder resist. 3-dimensional electromagnetic field simulation and S-parameter measurement are carried out in order to validate the effects of via cutting structure and VDDQ/VSSQ placement on the PDN impedance. New DRAM package substrate has a superior PDN impedance with a wide frequency range. This result shows that via cutting structure and power/ground placement are effective in reducing the PDN impedance.

COG (Chip On Glass) Bonding Technology for Flat Panel Display Using Induction Heating Body in AC Magnetic Field (교류자기장에 의한 유도가열체를 이용한 평판 디스플레이용 COG (Chip On Glass) 접속기술)

  • Lee Yoon-Hee;Lee Kwang-Yong;Oh Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.12 no.4 s.37
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    • pp.315-321
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    • 2005
  • Chip-on-glass technology to attach IC chip directly on the glass substrate of flat panel display was studied by using induction heating body in AC magnetic field. With applying magnetic field of 230 Oe at 14 kHz, the temperature of an induction heating body made with Cu electrodeposited film of 5 mm${\times}$5 mm size and $600{\mu}m$ thickness reached to $250^{\circ}C$ within 60 seconds. However, the temperature of the glass substrate was maintained below $100^{\circ}C$ at a distance larger than 2 mm from the Cu induction heating body. COG bonding was successfully accomplished with reflow of Sn-3.5Ag solder bumps by applying magnetic field of 230 Oe at 14 kHz for 120 seconds to a Cu induction heating body of 5mm${\times}$5mm size and $600{\mu}m$ thickness.

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Micro Joining Process Using Solderable Anisotropic Conductive Adhesive (Solderable 이방성 도전성 접착제를 이용한 마이크로 접합 프로세스)

  • Yim, Byung-Seung;Jeon, Sung-Ho;Song, Yong;Kim, Yeon-Hee;Kim, Joo-Heon;Kim, Jong-Min
    • Proceedings of the KWS Conference
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    • 2009.11a
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    • pp.73-73
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    • 2009
  • In this sutdy, a new class ACA(Anisotropic Conductive Adhesive) with low-melting-point alloy(LMPA) and self-organized interconnection method were developed. This developed self-organized interconnection method are achieved by the flow, melting, coalescence and wetting characteristics of the LMPA fillers in ACA. In order to observe self-interconnection characteristic, the QFP($14{\times}14{\times}2.7mm$ size and 1mm lead pitch) was used. Thermal characteristic of the ACA and temperature-dependant viscosity characteristics of the polymer were observed by differential scanning calorimetry(DSC) and torsional parallel rheometer, respectively. A electrical and mechanical characteristics of QFP bonding were measured using multimeter and pull tester, respectively. Wetting and coalescence characteristics of LMPA filler particles and morphology of conduction path were observed by microfocus X-ray inspection systems and cross-sectional optical microscope. As a result, the developed self-organized interconnection method has a good electrical characteristic($2.41m{\Omega}$) and bonding strength(17.19N) by metallurgical interconnection of molten solder particles in ACA.

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A Study of Warpage Analysis According to Influence Factors in FOWLP Structure (FOWLP 구조의 영향 인자에 따른 휨 현상 해석 연구)

  • Jung, Cheong-Ha;Seo, Won;Kim, Gu-Sung
    • Journal of the Semiconductor & Display Technology
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    • v.17 no.4
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    • pp.42-45
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    • 2018
  • As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

Uncooled Microbolometer FPA Sensor with Wafer-Level Vacuum Packaging (웨이퍼 레벨 진공 패키징 비냉각형 마이크로볼로미터 열화상 센서 개발)

  • Ahn, Misook;Han, Yong-Hee
    • Journal of Sensor Science and Technology
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    • v.27 no.5
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    • pp.300-305
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    • 2018
  • The uncooled microbolometer thermal sensor for low cost and mass volume was designed to target the new infrared market that includes smart device, automotive, energy management, and so on. The microbolometer sensor features 80x60 pixels low-resolution format and enables the use of wafer-level vacuum packaging (WLVP) technology. Read-out IC (ROIC) implements infrared signal detection and offset correction for fixed pattern noise (FPN) using an internal digital to analog convertor (DAC) value control function. A reliable WLVP thermal sensor was obtained with the design of lid wafer, the formation of Au80%wtSn20% eutectic solder, outgassing control and wafer to wafer bonding condition. The measurement of thermal conductance enables us to inspect the internal atmosphere condition of WLVP microbolometer sensor. The difference between the measurement value and design one is $3.6{\times}10-9$ [W/K] which indicates that thermal loss is mainly on account of floating legs. The mean time to failure (MTTF) of a WLVP thermal sensor is estimated to be about 10.2 years with a confidence level of 95 %. Reliability tests such as high temperature/low temperature, bump, vibration, etc. were also conducted. Devices were found to work properly after accelerated stress tests. A thermal camera with visible camera was developed. The thermal camera is available for non-contact temperature measurement providing an image that merged the thermal image and the visible image.

Laser Micro Soldering and Soldering Factors (레이저 마이크로 솔더링과 솔더링 인자)

  • Hwang, Seung Jun;Hwang, Sung Vin;Jung, Jae Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.27 no.3
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    • pp.1-8
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    • 2020
  • In this paper, the principles, characteristics and recent studies of the laser micro soldering are reviewed. The factors which influence laser micro welding and soldering are also included. Laser soldering is a non-contact process that transfers energy to solder joint by a precisely controlled laser beam. In recent electronics industry, the demands for laser soldering are increasing due to bonding for complex circuits and local heating in micro-joint. In laser soldering, there are several important factors like laser absorption, laser power, laser scanning speed, and etc, which affect laser solderability. The laser absorption ratio depends on materials, and each material has different absorption or reflectivity for the laser beam, which requires fine adjustment of the laser beam. Laser types and operating conditions are also important factors for laser soldering performance, and these are also reviewed.

The Wetting Properties of UBM-coated Si-wafer to the Lead-free Solders in Si-wafer/Bumps/Glass Flip-Chip Bonding System

  • Hong, Soon-Min;Park, Jae-Yong;Park, Chang-Bae;Jung, Jae-Pil;Kang, Choon-Sik
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.04a
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    • pp.74-79
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    • 2000
  • In an attempt to estimate the wetting properties of wettable metal layers by wetting balance method, an analysis of wetting curves of the coating layer was performed. Based on the analysis, wetting properties of UBM-coated Si-plate were estimated by the new wettability indices. The wetting curves of the one and both sides-coated UBM layers have the similar shape and show the similar tendency to the temperature. So the wetting property estimation of one side coating is possible with wetting balance method. For UBM of Si-chip, Cr/Cu/Au UBM is better than Ti/Ni/Au in the point of wetting time. At general reflow temperature, the wettability of high melting point solders(Sn-Sb, Sn-Ag) is better than that of few melting point ones(Sn-Bi, Sn-In).The contact angle of the one side coated plate to the solder can be calculated from the farce balance equation by measuring the static state force and the tilt angle.

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Thermal Fatigue Analysis of Wafer Level Embedded SiP by Changing Mold Compounds and Chip Sizes (몰드물성 종류 및 칩 크기 변화에 따른 웨이퍼 레벨 Sip에서의 열 피로 해석)

  • Jang, Chong Min;Kim, Seong Keol
    • Journal of the Korean Society of Manufacturing Technology Engineers
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    • v.22 no.3_1spc
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    • pp.504-508
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    • 2013
  • This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

Laser Micro-Joining and Soldering (레이저 마이크로 접합 및 솔더링)

  • Hwang, Seung Jun;Kang, Hye Jun;Kim, Jeng O;Jung, Jae Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.26 no.3
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    • pp.7-13
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    • 2019
  • In this paper, the principles, types and characteristics of the laser and laser soldering are introduced. Laser soldering methods for electronics, metals, semiconductors are also presented. Laser soldering is a non-contact process that transfers energy to solder joint by a precisely controlled beam. Demands for laser soldering are increasing due to bonding for complex circuits and local heating in micro joint. Laser absorption ratio depends on materials, and each material has different absorption or reflectivity of the laser beam, which requires fine adjustment of the laser beam. Laser types and operating conditions are also important factors for laser soldering performance. In this paper, the performance of Nd:YAG laser soldering is compared to the hot blast reflow. Meanwhile, a diode laser gives different wavelength and smaller parts with high performance, but it has various reliability issues such as heat loss, high power, and cooling technology. These issues need to be improved in the future, and further studies for laser micro-joining and soldering are required.

Fabrication of 6-superconducting layered HTS wire for high engineering critical current density

  • Kim, Gwantae;Ha, Hongsoo;Kim, Hosup;Oh, Sangsoo;Lee, Jaehun;Moon, Seunghyun
    • Progress in Superconductivity and Cryogenics
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    • v.23 no.4
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    • pp.10-13
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    • 2021
  • Recently, cable conductors composed of numerous coated conductors have been developed to transport huge current for large-scale applications, for example accelerators and fusion reactors. Various cable conductors such as CORC (Conductor on round core), Roebel Cable, and TSTC (Twisted stacked tape cable) have been designed and tested to apply for large-scale applications. But, these cable conductors cannot improve the engineering critical current density (Je) because they are made by simple stacking of coated conductors. In this study, multi-HTS (High temperature superconductor) layers on one substrate (MHOS) wire was fabricated to increase the engineering critical current density by using the exfoliation of superconducting layer from substrate and silver diffusion bonding method. By the repetition of these processes, the 10 m long 6-layer MHOS conductor was successfully fabricated without any intermediate layers like buffer or solder. 6-layer MHOS conductor exhibited a high critical current of 2,460A/12mm-w. and high engineering critical current density of 1,367A/mm2 at liquid nitrogen temperature.