• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.5-5
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• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.137-137
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• 2009

Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.4
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• pp.202-209
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• 2002

The stochiometric mix of evaporating materials for the $CuInSe_2$single crystal thin films was prepared from horizontal furnace. To obtain the single crystal thin films, $CuInSe_2$compound crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by the Hot Wall Epitaxy (HWE) system. The source and substrate temperature were $620^{\circ}C$ and $410^{\circ}C$, respectively. The crystalline structure of single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction (DCXD). The carrier density and mobility of $CuInSe_2$single crystal thin films measured from Hall effect by van der Pauw method. From the photocurrent spectrum by illumination of perpendicular light on the c-axis of the $CuInSe_2$single crystal thin film, we have found that the values of spin orbit splitting $\Delta$So and the crystal field splitting $\Delta$Cr. From the photoluminescence measurement on $CuInSe_2$single crystal thin film, we observed free exciton ($E_x$) existing only high quality crystal and neutral bound exciton ($A^{\circ}$, X) having very strong peak intensity. Then, the full-width-at-half-maximum (FWHM) and binding energy of neutral donor bound exciton were 7 meV and 5.9 meV, respectivity. By haynes rule, an activation energy of impurity was 59 meV.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.11-11
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• 2010

Thin-film-transistors (TFTs) that can be deposited at low temperature have recently attracted lots of applications such as sensors, solar cell and displays, because of the great flexible electronics and transparent. Transparent and flexible transistors are being required that high mobility and large-area uniformity at low temperature [1]. But, unfortunately most of TFT structures are used to be $SiO_2$ as gate dielectric layer. The $SiO_2$ has disadvantaged that it is required to high driving voltage to achieve the same operating efficiency compared with other high-k materials and its thickness is thicker than high-k materials [2]. To solve this problem, we find lots of high-k materials as $HfO_2$, $ZrO_2$, $SiN_x$, $TiO_2$, $Al_2O_3$. Among the High-k materials, $Al_2O_3$ is one of the outstanding materials due to its properties are high dielectric constant ( ~9 ), relatively low leakage current, wide bandgap ( 8.7 eV ) and good device stability. For the realization of flexible displays, all processes should be performed at very low temperatures, but low temperature $Al_2O_3$ grown by sputtering showed deteriorated electrical performance. Further decrease in growth temperature induces a high density of charge traps in the gate oxide/channel. This study investigated the effect of growth temperatures of ALD grown $Al_2O_3$ layers on the TFT device performance. The ALD deposition showed high conformal and defect-free dielectric layers at low temperature compared with other deposition equipments [2]. After ITO was wet-chemically etched with HCl : $HNO_3$ = 3:1, $Al_2O_3$ layer was deposited by ALD at various growth temperatures or lift-off process. Amorphous InGaZnO channel layers were deposited by rf magnetron sputtering at a working pressure of 3 mTorr and $O_2$/Ar (1/29 sccm). The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. The TFT devices were heat-treated in a furnace at $300^{\circ}C$ and nitrogen atmosphere for 1 hour by rapid thermal treatment. The electrical properties of the oxide TFTs were measured using semiconductor parameter analyzer (4145B), and LCR meter.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.143-144
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• 2010

3-5족 화합물 반도체를 이용한 집광형 삼중 접합 태양전지는 40% 이상의 광변환 효율로 많은 주목을 받고 있다[1]. 삼중 접합 태양전지의 하부 셀은 기계적 강도가 높고 장파장을 흡수할 수 있는 Ge이 사용된다. Ge위에 성장될 III-V족 단결정막으로서 Ge과 격자상수가 일치하는 GaInP나 GaAs가 적합하고, 성장 중 V족 원소의 열확산으로 인해 Ge과 pn접합을 형성하게 된다. 이때 GaInP의 P의 경우 GaAs의 As보다 확산계수가 낮아 태양전지 변환효율향상에 유리한 얇은 접합 형성이 가능하고, 표면 에칭효과가 적기 때문에 GaInP를 단결정막으로 선택하여 p-type Ge기판 위 성장으로 단일접합 Ge구조 제작이 가능하다. 하지만 이종접합 구조 성장으로 인해 발생한 계면사이의 전위나 미세결함들이 결정막내부에 존재하게 되며 이러한 결함들은 광학소자 응용 시 비발광 센터로 작용할 뿐 아니라 소자의 누설전류를 증가시키는 원인으로 작용하여 태양전지 변환효율을 감소시키게 된다. 이에 결함감소를 통해 소자의 전기적 특성을 향상시키고자 수소 열처리나 플라즈마 공정을 통해 수소 원자를 박막내부로 확산시키고, 계면이나 박막 내 결함들과 결합시킴으로서 결함들의 비활성화를 유도하는 연구가 많이 진행되어 왔다 [2][3]. 하지만, 격자불일치를 갖는 GaInP/Ge 구조에 대한 수소 열처리 및 불순물 준위의 거동에 대한 연구는 많이 진행되어 있지 않다. 따라서 본 연구에서는 Ga0.45In0.55P/Ge구조에 수소 열처리 공정을 적용을 통하여 단결정막 내부 및 계면에서의 결함밀도를 제어하고 이를 통해 태양 전지의 변환효율을 향상시키고자 한다. <111> 방향으로 $6^{\circ}C$기울어진 p-type Ge(100) 기판 위에 유기금속화학증착법 (MOCVD)을 통해 Si이 도핑된 200 nm의 n-type GaInP층을 성장하여 Ge과 단일접합 n-p 구조를 제작하였다. 제작된 GaInP/Ge구조를 furnace에서 250도에서 90~150분간 시간변화를 주어 수소열처리 공정을 진행하였다. 저온 photoluminescence를 통해 GaInP층의 광학적 특성 변화를 관찰한 결과, 1.872 eV에서 free-exciton peak과 1.761 eV에서 Si 도펀트 saturation에 의해 발생된 D-A (Donor to Acceptor)천이로 판단되는 peak을 검출할 수 있었다. 수소 열처리 시간이 증가함에 따라 free-exciton peak 세기 증가와 반가폭 감소를 확인하였고, D-A peak이 사라지는 것을 관찰할 수 있었다. 이러한 결과는 수소 열처리에 따른 단결정막 내부의 수소원자들이 얕은 불순물(shallow impurity) 들로 작용하는 도펀트들이나, 깊은 준위결함(deep level defect)으로 작용하는 계면근처의 전위, 미세결함들과의 결합으로 결함 비활성화를 야기해 발광세기와 결정질 향상효과를 보인 것으로 판단된다. 본 발표에서는 상술한 결과를 바탕으로 한 수소 열처리를 통한 박막 및 계면에서의 결함준위의 거동에 대한 광분석 결과가 논의될 것이다.

• Journal of the Korean Vacuum Society
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• v.22 no.5
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• pp.238-244
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• 2013

Doping process using laser is an important process in fabrication of solar cell for heat treatment. However, the process of using the furnace is difficult to form a selective emitter doping region. The case of using a selective emitter laser doping is required an expensive laser equipment and induce the wafer's structure damage due to high temperature. This study, we fabricated a new costly plasma source. Through this, we research the selective emitter doping. We fabricated that the atmospheric pressure plasma jet injected Ar gas is inputted a low frequency (a few tens kHz). We used shallow doping wafers existing PSG (Phosphorus Silicate Glass) on the shallow doping CZ P-type wafer. Atmospheric plasma treatment time was 15 s and 30 s, and current for making the plasma is 40 mA and 70 mA. We investigated a doping profile by using SIMS (Secondary Ion Mass Spectroscopy) and we grasp the sheet resistance of electrical character by using doping profile. As result of experiment, prolonged doping process time and highly plasma current occur a deeper doping depth, moreover improve sheet resistance. We grasped the wafer's surface damage after atmospheric pressure plasma doping by using SEM (Scanning Electron Microscopy). We check that wafer's surface is not changed after plasma doping and atmospheric pressure doping width is broaden by increase of plasma treatment time and current.