• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.605-606
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• 2008

The distance detection system receives stereo video input through 2 CCD cameras. Using a decoder, the image is changed to the YCbCr4:2:2 format and only the Y signal is saved in the 4*256*8bit shift register of the Dual-Port SRAM. As a result of the matching procedure, the Depth value, which is the distance information, is saved in SRAM, and the Depth Map is made and output to the TFT-LCD screen.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.936-939
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• 2002

FPCA is the necessary device to design of hardware at present, it is researched on many ways of applying to design caused by expansion of capacity in recent years. One of these applying ways is SoC (System on a Chip) that is proposed for realizing the basic function of a system. For realizing SoC efficiently, IP (Intellectual property) is very important and developed for re-use of hardware. A MPU for built-in exists as an IP. But almost of MPUs at present as an IPs are lengthy and large-scale for using embedded-application. Furthermore, the function of executing specific treatment critically is required to embedded MPU. We propose a flexible and small scale MPU and its design method.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06d
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• pp.24-27
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• 2011

최근 스마트 폰 등 모바일 기기의 폭발적인 성장에 의해 내장 프로세서인 ARM 프로세서 기반 기기들이 활발히 개발되어 사용되고 있다. 이에 따라 상대적으로 저성능, 저 전력화에 치중하였던 내장 프로세서도 고성능화를 위한 고속 동작 및 멀티코어 프로세서를 개발하여 사용하게 되었으며, 메모리 동작 속도 역시 빠르게 발전하고 있다. 특히 모바일 기기 등에 사용 되는 저전력 메모리인 LPDDR2 소자 등의 개발에 따라 빠른 동작 속도를 가지도록 개발되고 있다. 그러나 시스템 온 칩(SoC, System on Chip) 형태로 제작되는 ARM 프로세서 기반의 SoC는 다양한 하드웨어 가속기 등을 함께 내장하고 있고, 저 전력화를 위한 버스 구조 등에 의하여 온 칩 버스의 속도 향상이 고성능 범용 시스템에 비하여 낮은 수준이다. 본 연구에서는 이러한 점을 고려하여, 프로세서 코어와 메모리 소자의 동작 속도 향상에 의하여 얻을 수 있는 성능 향상과, 상대적으로 낮은 버스 동작 속도에 의하여 저하되는 성능의 정도를 분석하고 이를 극복하기 위한 방안을 검토하였다.

• Environmental Engineering Research
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• v.10 no.1
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• pp.31-37
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• 2005

The selective catalytic experiments using both sulfated/sulfur-free titania and V2O5/TiO2 catalysts have been conducted for NO reduction by NH3 in a packed-bed, down-flow reactor. The sulfated and vanadia loaded titania exhibited higher activity for NO removal than the sulfur-free catalysts, where > 90% NO removal was achieved over the sulfated V2O5/TiO2 catalyst between 280∼500 C. The surface structure of vanadia species on the catalyst surface played a critical role in the high performance of catalysts in which the existence of monomeric/polymeric vanadate is revealed by Raman spectra studies. Water vapor and SO2 were added to the reacting system for the catalyst deactivation tests. At higher temperatures (T ≥ 350 C), little deactivation was observed over the sulfated V2O5/TiO2 catalysts, showing good durability against SO2 and water vapor, which is compared with deactivation at lower temperatures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• Journal of the Korea Society of Computer and Information
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• v.18 no.8
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• pp.33-41
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• 2013

Intelligent automobile technology and IT convergence, the development of new imaging technology media applications based on open source Android installed on tracked, wheeled smart phone application technology and the development of intelligent vehicles as a new paradigm a lot of research and development being made. Android-based intelligent automotive applications, technology, and evolved into the center of a set of various multimedia technologies move beyond the limits of the means of each of multimedia platforms, services and applications that have been developed in such a distributed environment, has been developed according to a variety of services through technology mobile terminal device technology is an absolute requirement. In this paper, SVC Codec, real-time video and graphics processing and SoC design intelligent vehicles middleware applications with monolithic system specification through Android-based design of intelligent vehicles dedicated middleware research experiments on open platforms, and provides various terminal services functions SoC based on a newly designed and standardized interface analysis techniques in this study were verified through experiments.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.225-234
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• 2019

By using the Triboelectric nanogenerators, known as TENG, we can take advantages of high conversion efficiency and continuous power output even with small vibrating energy sources. Nonlinear energy extraction techniques for Triboelectric vibration energy harvesting usually requires synchronized active electronic switches in most electronic interface circuits. This study presents a nonlinear energy harvesting with high energy conversion efficiency to harvest and save energies from human active motions. Moreover, the proposed design can harvest and store energy from sway motions around different directions on a horizontal plane efficiently. Finally, we conducted a comparative analysis of a multi-mode energy storage board developed by a silicon-based piezoelectricity and a transparent TENG cell. As a result, the experiment showed power generation of about 49.2mW/count from theses multi-fully harvesting source with provision of stable energy storages.

• Fisheries and Aquatic Sciences
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• v.18 no.2
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• pp.131-135
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• 2015

Two new bitter-tasting cyclic peptides comprising six amino acids, namely gamakamide C and D, were isolated from cultured oysters Crassostrea gigas. Dimethylaminoazobenzene sulfonyl-amino acid analysis detected Val and Leu in gamakamide C and Ile and Leu in gamakamide D. The molecular formula of gamakamide C was determined as $C_{43}H_{60}N_{7}O_8S$ by high-resolution fast atom bombardment mass spectroscopy (HR FAB-MS) ($[M+H]^+m/z822.4200{\Delta}-2.4mmu$), and that of gamakamide D was determined as $C_{43}H_{62}N_7O_8S$ by HR FAB-MS ($[M+H]^+m/z836.4379{\Delta}-2.0mmu$). Comparison of amino acid analyses and fragment ions by MS/MS among gamakamide C, D, and E (known), the structures of gamakamide C and D were confirmed $as-{\small{L}}-Val-{\small{L}}-Met(SO)-{\small{L}}-NMe-Phe-{\small{L}}-Leu-{\small{D}}-Lys-{\small{L}}-Phe-$ and $-{\small{L}}-Ile-{\small{L}}-Met(SO)-{\small{L}}-NMe-Phe-{\small{L}}-Leu-{\small{D}}-Lys-{\small{L}}-Phe-$, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.3
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• pp.166-175
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• 2024

In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.286-292
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• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.