• Journal of the Korean Electrochemical Society
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• v.3 no.4
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• pp.196-199
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• 2000

Electroless plating is the desirable surface treatment method which is being widely used to all kinds of material such as requiring corrosion resistance, wear resistance and conductivity, especially plating of nonconductive material. Electroless nickel deposit has particular characteristics including non-magnetic property, amorphous structure, wear resistance, corrosion protection and thermal stability. In this study, electroless nickel plating was studied with an change in hardness and corrosion resistance of electroless nickel-phosphorus deposit depending on heat treatment. The highest hardness value was obtained by heat treatment at $500^{\circ}C$ Corrosion resistance of deposit, which had been heated at $300^{\circ}C$, was excellent when it was immersed in 1M $H_2SO_4$ solution for 60 hrs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2731-2740
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• 2012

ASIC(application specific integrated circuit) process is a set of various technologies for fabricating a chip. Generally there have been many researches for RTL design, synthesis, floor plan & routing, low power scheme, clock tree synthesis, and testability which are widely researched in recent. In this paper we propose a new methodology of power strap routing in basis of design experience and experiment. First the power strap for vertical VDD and VSS and horizontal VDD and VSS is routed, and then after the problems which are generated in this process are analyzed, we propose a new process for resolving them. For this, the strap guide is inserted to protect the unnecessary strap routing and dumped for next steps. Next the unnecessary power straps which are generated the first inserting process are removed, and the pre-routing is performed for the macro cells. Finally the resultant power straps are routed using the dumped routing guide. Through the proposed process we identified the efficient and stable route of the power straps.

• Journal of the Korean Recycled Construction Resources Institute
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• v.9 no.1
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• pp.92-99
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• 2021

CaO-based by-products composed of CaO, SO3, Al2O3, etc. are generally used as raw materials for CaO compounds. When applied to the recovered water of ready-mixed concrete, the hydration reaction of the powder material is accelerated and concrete performance can be improved. In this study, activated sludge was prepared to apply to the recovered water of ready-mixed concrete by mixing CaO-based hot-rolled slag(C12A7) in the recycling water of ready-m ixed concrete. Cem ent paste setting time and mortar compressive strength performance tests confirmed the effect on the hydration reaction. Therefore, the possibility of concrete application using activated sludge was confirmed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.360-363
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• 2022

According to the 2018 Kaggle ML & DS Survey, among the proportions of frameworks for machine learning and data science, TensorFlow and Keras each account for 41.82%. It was found to be 34.09%, and in the case of development programming, it is confirmed that about 82% use Python. A significant number of machine learning and deep learning structures utilize the Keras framework and Python, but in the case of Python, distribution and execution are limited to the Python script environment due to the script language, so it is judged that it is difficult to operate in various environments. This paper implemented a machine learning and deep learning system using C# and Keras running in Visual Studio 2019. Using the Mnist dataset, 100 tests were performed in Python 3.8,2 and C# .NET 5.0 environments, and the minimum time for Python was 1.86 seconds, the maximum time was 2.38 seconds, and the average time was 1.98 seconds. Time 1.78 seconds, maximum time 2.11 seconds, average time 1.85 seconds, total time 37.02 seconds. As a result of the experiment, the performance of C# improved by about 6% compared to Python, and it is expected that the utilization will be high because executable files can be extracted.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• The KIPS Transactions:PartC
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• v.15C no.5
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• pp.409-418
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• 2008

In this paper, we programed the PPP(Point-to-Point Protocol) used in embedded application environments for Globalstar Satellite Modem. There are number of satellite communication systems such as Orbcomm, Globalstar, Inmarsat and etc. But each satellite data service have provided a communication interface only for their own data links. A data communication link is needed to communicate with Globalstar satellite service. Globalstar communication system uses PPP to establish data communication link, so we implemented the embedded processor based PPP protocol. The user terminal equipment also designed in this paper has various input/output devices and sensors applicable to any user specific application. The proposed PPP program works well with Globalstar data communication link through experimental tests.

• Journal of Intelligence and Information Systems
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• v.15 no.3
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• pp.17-29
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• 2009

C programming is a main programming for the Educational Robot Arm which is based on AVR ATmega128. The development environment is not integrated, so it is complex and difficult to study for middle or high school students who want to learn programming and control the educational robot arm. Furthermore, there is no debug and testing environment support. This paper presents a Java-based development platform for the educational robot arm. This platform includes: an up-to-date tiny Java Virtual Machine (NanoVM) for the educational robot arm; An Eclipse based Java integrated development environment as an Eclipse plug-in; a 3D simulator on the PCs to support testing and debugging programs without real robots. The Java programming environment makes development for educational robot arm easier for students.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.4-6
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• 2014

본 논문에서는 하드웨어 HEVC 디코더의 움직임 보상 모듈의 구조를 제안한다. 제안된 구조를 갖는 움직임 보상 모듈은 하드웨어 처리 싸이클 수와 내부메모리 크기를 감소시키기 위해 하나의 코딩 유닛을 그보다 작은 여러 개의 블록으로 분할하여 처리할 수 있다. 제안된 움직임 보상 구조는 캐시를 통해 외부 메모리에 접근하여 참조 픽쳐를 로딩하는 단계와 보간 필터를 거쳐 예측 샘플을 생성하는 단계로 내부-파이프라인을 구성하며 코딩 유닛의 크기에 따라 내부-파이프라인에서 처리할 블록의 크기를 결정한다. 본 논문에서는 코딩 유닛 분할의 기준이 되는 블록 크기를 결정하기 위한 절충사항에 대해서도 논의한다. 제안된 구조의 효율성을 판단하기 위해 구현된 움직임 보상 모듈을 RTL 시뮬레이션 및 FPGA 보드 검증을 통해 테스트 하였으며, SoC 로 제작될 경우 초당 249 Mpixel 을 처리하여 4K-UHD 시퀀스의 실시간 디코딩이 가능한 것으로 판단되었다.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.232-237
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• 2007

컴퓨터 시스템의 설계는 알고리즘 수준의 모델링에서부터 시제품 수준까지 시스템을 구체화해 나가는 일련의 과정이다. 시스템 구현의 구체화 과정에는 단순하고 반복적인 구현이 많이 포함되며, 이 과정에서 많은 오류가 발생한다. 이러한 오류는 개발자가 알고리즘 수준에서는 드러나지 않는 복잡하고 아키텍처 의존적인 하드웨어-소프트웨어 동기화 메커니즘의 개발과 같은 시스템 구현의 구체화 과정을 모두 떠안고 있기 때문에 발생하는 것이다. 이 논문에서는, 이러한 문제를 극복하기 위하여, 알고리즘을 데이터 플로우로 모델링하면 이로부터 합성 가능한 하드웨어 플랫폼과 동기화 로직, 그리고 동기화를 위한 드라이버 소프트웨어 일제를 자동 생성하는 설계 과정을 제시하고자 한다. 제시된 설계 과정은 자체 개발한 통합 설계 도구 상에 구현되었으며, 이를 통해서 개발된 H.263 디코더 예제를 상용의 RTL 통합 시뮬레이션 도구인 Seamless CVE와, SoC 프로토타이핑 환경인 Altera Excalibur 시스템 상에서 테스트하여 그 완성도를 검증하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.10a
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• pp.201-203
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• 2019

5G 시스템은 혁신적인 발전을 거듭하며 강력해진 기술 표준을 근간으로 초광대역 이동형 데이터 서비스, 대규모 사물통신 서비스 등을 제공하고 있다. 본 논문에서는 SW를 기반으로 한 5G의 기술 개발 방법론을 제안한다. 또, 실제 환경에서 차세대 모바일 네트워크의 성능 분석이 가능한 SW 기반의 시스템 레벨 테스트베드 및 모니터링 프로그램을 OAI(Openairinterface) 5G 연구 단체의 오픈소스를 이용하여 구현한다. 기존 하드웨어 위주의 단일 칩 시스템(SoC)을 이용한 구현은 손상되기가 쉽고 유지보수가 힘들다는 단점이 있다. 하지만 기존 하드웨어 칩을 소프트웨어 기반인 소스코드로 구현하면 유지 보수가 용이하다는 장점뿐만 아니라 하드웨어가 변경되더라도 다른 하드웨어에 호환되는 이식성 때문에 생산성이 높아지며 비용 절감의 효과도 기대할 수 있다.