• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송∙미디어공학회 2019년도 하계학술대회
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• pp.98-101
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• 2019

At present, deep convolutional neural networks have made a very important contribution in single-image super-resolution. Through the learning of the neural networks, the features of input images are transformed and combined to establish a nonlinear mapping of low-resolution images to high-resolution images. Some previous methods are difficult to train and take up a lot of memory. In this paper, we proposed a simple and compact deep recursive residual network learning the features for single image super resolution. Global residual learning and local residual learning are used to reduce the problems of training deep neural networks. And the recursive structure controls the number of parameters to save memory. Experimental results show that the proposed method improved image qualities that occur in previous methods.

• Journal of Information Processing Systems
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• 제18권1호
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• pp.12-25
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• 2022

In recent years, deep convolutional neural networks have made significant progress in the research of single image super-resolution. However, it is difficult to be applied in practical computing terminals or embedded devices due to a large number of parameters and computational effort. To balance these problems, we propose CSRNet, a lightweight neural network based on channel split residual learning structure, to reconstruct highresolution images from low-resolution images. Lightweight refers to designing a neural network with fewer parameters and a simplified structure for lower memory consumption and faster inference speed. At the same time, it is ensured that the performance of recovering high-resolution images is not degraded. In CSRNet, we reduce the parameters and computation by channel split residual learning. Simultaneously, we propose a double-upsampling network structure to improve the performance of the lightweight super-resolution network and make it easy to train. Finally, we propose a new evaluation metric for the lightweight approaches named 100_FPS. Experiments show that our proposed CSRNet not only speeds up the inference of the neural network and reduces memory consumption, but also performs well on single image super-resolution.

• 재활치료과학
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• 제3권1호
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• pp.57-65
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• 2014

목적 : 본 연구는 뇌졸중 환자를 대상으로 스마트폰 인지 어플리케이션을 이용한 집중력과 기억력 효과를 알아보고자 하였다. 연구방법 : 단일사례연구 방법 중 ABA 설계를 사용하여 기초선 A 5회, 중재기 B 10회, 기초선 A' 5회기로 총 20회기를 총 4주에 걸쳐 적용하였다. 기초선 A와 기초선 A' 기간에는 별도의 중재를 하지 않았고 중재기 B 기간 동안 '기억의 달인(숫자, 도형, 과일 모드)'과 'Matching cute animals'라는 어플리케이션을 통해 중재하였다. 전 회기에 걸쳐 '기억의 달인(랜덤 모드)'과 'Memory free(그림외우기)'어플리케이션을 이용해 기억력과 집중력을 평가하였다. 결과 자료는 그래프와 기술통계량으로 제시하였다. 결과 : 회기 별 실시한 기억력과 집중력 평가 결과, 기초선 A와 기초선 A' 기간보다 중재기 B 기간 동안 집중력과 기억력의 향상을 보였고, 중재 전과 후에 실시한 평가에서도 중재 후의 평가에서 집중력과 기억력의 향상을 보였다. 결론 : 본 연구를 통해 검증된 스마트폰 어플리케이션을 이용한 중재 효과가 임상적 근거를 제공하는데 유용하게 사용되기를 기대하며, 향후 연구에서는 더 많은 표본을 대상으로 장시간에 걸쳐 시행한 연구가 진행될 필요가 있다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.241-241
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• 2010

New non-volatile memory with high density and high work-function metal nano-dots, MND (Metal Nano-Dot) memory, was proposed and fundamental characteristics of MND capacitor were evaluated. In this work, nano-dot layer of FePt with high density and high work-function (~5.2eV) was fabricated as a charge storage site in non-volatile memory, and its electrical characteristics were evaluated for the possibility of non-volatile memory in view of cell operation by Fowler-Nordheim (FN)-tunneling. Here, nano-dot FePt layer was controlled as a uniform single layer with dot size of under ~ 2nm and dot density of ${\sim}\;1.2{\times}10^{13}/cm^2$. Electrical measurements of MOS structure with FePt nano-dot layer shows threshold voltage window of ~ 6V using FN programming and erasing, which is satisfied with operation of the non-volatile memory. Furthermore, this structure provides better data retention characteristics compared to other metal dot materials with the similar dot density in our experiments. From these results, it is expected that this non-volatile memory using FePt nano-dot layer with high dot density and high work-function can be one of candidate structures for the future non-volatile memory.

• Journal of Information Processing Systems
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• 제15권1호
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• pp.151-158
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• 2019

With the recent advances of memory technologies, high-performance non-volatile memories such as non-volatile dual in-line memory module (NVDIMM) have begun to be used as an addition or an alternative to server-side storages. When these memory bus-connected storages (MBSs) are installed over non-uniform memory access (NUMA) servers, the distance between NUMA nodes and MBSs is one of the crucial factors that influence file processing performance, because the access latency of a NUMA system varies depending on its distance from the NUMA nodes. This paper presents the design and implementation of a high-performance logical volume manager for MBSs, called MBS-LVM, when multiple MBSs are scattered over a NUMA server. The MBS-LVM consolidates the address space of each MBS into a single global address space and dynamically utilizes storage spaces such that each thread can access an MBS with the lowest latency possible. We implemented the MBS-LVM in the Linux kernel and evaluated its performance by porting it over the tmpfs, a memory-based file system widely used in Linux. The results of the benchmarking show that the write performance of the tmpfs using MBS-LVM has been improved by up to twenty times against the original tmpfs over a NUMA server with four nodes.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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• pp.35-38
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• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• 한국인터넷방송통신학회논문지
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• 제22권1호
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• pp.71-76
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• 2022

버퍼 캐시는 스토리지의 느린 속도를 완충하는 중요한 역할을 하지만, 데이터의 유실을 막기 위한 주기적인 플러시 연산으로 인해 스마트폰에서 그 효과가 크게 떨어진다. 본 논문에서는 소량의 영속 메모리에 선택적인 플러시 정책을 적용하여 스마트폰 버퍼 캐시의 플러시 오버헤드를 크게 줄일 수 있음을 보인다. 이는 스마트폰 앱의 I/O 분석 결과 대부분의 파일 쓰기가 소량의 핫 데이터에 집중돼 있는 반면 상당 부분의 파일 데이터는 1회성 쓰기에 국한한다는 점에 근거한다. 제안하는 기법은 플러시 상황 발생 시 자주 수정되는 데이터를 영속 메모리로 우회 플러시하고 그렇지 않은 데이터만을 스토리지로 플러시한다. 이를 통해 스토리지 쓰기량을 크게 줄이는 동시에 영속 메모리의 공간 효율성을 높인다. 인기 있는 스마트폰 앱의 I/O 트레이스를 이용한 재현 실험을 통해 제안하는 기법이 스토리지 쓰기량을 평균 25.8%, 최대 37.8%까지 줄임을 보인다.

• 한국멀티미디어학회논문지
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• 제2권1호
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• pp.80-88
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• 1999

본 논문에서는 컴퓨터 그래픽스 연산의 메모리 액세스 속도를 개선하는 새로운 메모리 구조를 갖는 그래픽스 전용 메모리(SMGRA, Special Memory for GRAphics)를 제안한다. 제안된 그래픽스 전용 메모리는 사각형 영역의 화소를 동시에 처리할수 있는 Whelan이 제안한 장방형 어레이 메모리 구조를개선하여 주소디코딩시 간을 줄여주고 멀티플렉싱 기법을 사용하여 주소핀 수를 1/2로 줄인다 또한, 그래픽스 전용 메모리는 간단한 연산 로직을 가지므로 3차원 그래픽스 처리시 요구되는 읽기-수정-쓰기 메모리 사이클을 쓰기 메모리 사이클 로 대체하므로 프레임 버퍼 액세스 속도를 개선한다.

• 전기학회논문지
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• 제60권5호
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• pp.1036-1042
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• 2011

This paper presents an algorithm that conducts automatic memory scrubbing operated by dedicated hardwares. The proposed algorithm is designed so that it can scrub entire memory in a given scrub period, while minimally affecting the execution of flight softwares. The scrub controller is constructed in a form of state machines, which have two execution modes - normal mode and burst mode. The deadline event generator and period tick generator are designed in a separate way to support the behavior of the scrub controller. The proposed controller is implemented in VHDL code to validate its applicability. A simple version of the controller is also applied to mass memory modules used in STSAT-3.

• 대한임베디드공학회논문지
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• 제11권2호
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• pp.107-116
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• 2016

Density of Phase-Change Memory (PCM) devices has been doubled through the employment of multi-level cell (MLC) technology. However, this doubled-capacity comes in the expense of severe performance degradation, as compared to the conventional single-level cell (SLC) PCM. This negative effect on the performance of the MLC PCM detracts from the potential benefits of the MLC PCM. This paper introduces an efficient way of minimizing the performance degradation while maximizing the capacity benefits of the MLC PCM. To this end, we propose a location-aware hybrid management of SLC and MLC in compressed PCM main memory systems. Our trace-driven simulations using real application workloads demonstrate that the proposed technique enhances the performance and energy consumption by 45.1% and 46.5%, respectively, on the average, over the conventional technique that only uses a MLC PCM.