• Journal of Korean Society of Transportation
• /
• v.18 no.1
• /
• pp.47-59
• /
• 2000

The purpose of this study is to develop travel-time estimation model using neural networks and prediction model using neural networks and kalman-filtering technique. The data used in this study are travel speed collected from inductive loop vehicle detection systems(VDS) and travel time collected from the toll collection system (TCS) between Seoul and Osan toll Plaza on the Seoul-Pusan Expressway. Two models, one for travel-time estimation and the other for travel-time Prediction were developed. Application cases of each model were divided into two cases, so-called, a single-region and a multiple-region. because of the different characteristics of travel behavior shown on each region. For the evaluation of the travel time estimation and Prediction models, two Parameters. i.e. mode and mean were compared using five-minute interval data sets. The test results show that mode was superior to mean in representing the relationship between speed and travel time. It is, however shown that mean value gives better results in case of insufficient data. It should be noted that the estimation and the Prediction of travel times based on the VDS data have been improved by using neural networks, because the waiting time at exit toll gates can be included for the estimation of travel time based on the VDS data by considering differences between VDS and TCS travel time Patterns in the models. In conclusion, the results show that the developed models decrease estimation and prediction errors. As a result of comparing the developed model with the existing model using the observed data, the equality coefficients of the developed model was average 88% and the existing model was average 68%. Thus, the developed model was improved minimum 17% and maximum 23% rather then existing model .

• The KIPS Transactions:PartA
• /
• v.11A no.3
• /
• pp.189-198
• /
• 2004

We consider the fault hamiltonian properties of m ${\times}$ n meshes with two wraparound links on the first row and the last row, denoted by M$_2$(m,n), (m$\geq$2, n$\geq$3). M$_2$(m,n), which is bipartite, with a single faulty link has a fault-free path of length mn-l(mn-2) between arbitrary two nodes if they both belong to the different(same) partite set. Compared with the previous works of P$_{m}$ ${\times}$C$_{n}$ , it also has these hamiltonian properties. Our result show that two additional wraparound links are sufficient for an m${\times}$n mesh to have such properties rather than m wraparound links. Also, M$_2$(m,n) is a spanning subgraph of many interconnection networks such as multidimensional meshes, recursive circulants, hypercubes, double loop networks, and k-ary n-cubcs. Thus, our results can be applied to discover fault-hamiltonicity of such interconnection networks. By applying hamiltonian properties of M$_2$(m,n) to 3-dimensional meshes, recursive circulants, and hypercubes, we obtain fault hamiltonian properties of these networks.

• Magazine of the Korean Society of Agricultural Engineers
• /
• v.18 no.2
• /
• pp.4116-4120
• /
• 1976

With the use of many rivers increased nearly to the capacity, the need for information concerning daily quantities of water and the total annual or seasonal runoff has became increased. A systematic record of the flow of a river is commonly made in terms of the mean daily discharge Since. a single observation of stage is converted into discharge by means of rating curve, it is essential that the stage discharge relations shall be accurately established. All rating curves have the looping effect due chiefly to channel storage and variation in surface slope. Loop rating curves are most characteristic on streams with somewhat flatter gradients and more constricted channels. The great majority of gauge readings are taken by unskilled observers once a day without any indication of whether the stage is rising or falling. Therefore, normal rating curves shall show one discharge for one gauge height, regardless of falling or rising stage. The above reasons call for the correction of the discharge measurements taken on either side of flood waves to the theoretical steady-state condition. The correction of the discharge measurement is to consider channel storage and variation in surface slope. (1) Channel storage As the surface elevation of a river rises, water is temporarily stored in the river channel. There fore, the actual discharge at the control section can be attained by substracting the rate of change of storage from the measured discharge. (2) Variation in surface slope From the Manning equation, the steady state discharge Q in a channel of given roughness and cross-section, is given as {{{{Q PROPTO SQRT { 1} }}}} When the slope is not equal, the actual discharge will be {{{{ { Q}_{r CDOT f } PROPTO SQRT { 1 +- TRIANGLE I} CDOT TRIANGLE I }}}} may be expressed in the form of {{{{ TRIANGLE I= { dh/dt} over {c } }}}} and the celerity is approximately equal to 1.3 times the mean watrr velocity. Therefore, The steady-state discharge can be estimated from the following equation. {{{{Q= { { Q}_{r CDOT f } } over { SQRT { (1 +- { A CDOT dh/dt} over {1.3 { Q}_{r CDOT f }I } )} } }}}} If a sufficient number of observations are available, an alternative procedure can be applied. A rating curve may be drawn as a median line through the uncorrected values. The values of {{{{ { 1} over {cI } }}}} can be yielded from the measured quantities of Qr$.$f and dh/dt by use of Eq. (7) and (8). From the 1/cI v. stage relationship, new vlues of 1/cI are obtained and inserted in Eq. (7) and (8) to yield the steady-state discharge Q. The new values of Q are then plotted against stage as the corrected steadystate curve.

• Journal of the Korean Magnetics Society
• /
• v.23 no.6
• /
• pp.200-204
• /
• 2013

In this study, we have fabricated magnetoresistive sensors of $50{\mu}m{\times}50{\mu}m$ cross type by trilayer structure of antiferromagnetic/nonmagnetic/ferromagnetic. The magnetic signal and magnetic domain of this sensor is measured. The sensor hysteresis loop is not in symmetrical at 0 Oe. This is may be due to the exchange coupling between ferromagnetic layer and anti ferromagnetic layer. This exchange bias value is 20 Oe. The sensor signal is measured at between the applied magnetic field and current. The sensor signal is measured between the applied magnetic field and current at $20^{\circ}$ and $90^{\circ}$ angles. The sensitivity of sensor signals is $20{\mu}V/Oe$ and $7{\mu}V/Oe$ at $20^{\circ}$ and $90^{\circ}$ angles, respectively. In addition, this sensor is also applied for the detection of magnetic bacteria at $20^{\circ}$ angle. From these results, we calculate the stray field of single bacteria is to be $5{\times}10^{-5}$Oe.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.12
• /
• pp.75-82
• /
• 2010

This paper presents a wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer for a multi-band single chip CMOS RFIC transceivers. A wideband VCO utilizes a 6-bit switched capacitor array bank for 2340~3940 MHz frequency range. VCO frequency calibration circuit is designed for optimal capacitor bank code selection before phase locking process. It finishes the calibration process in $2{\mu}s$ over the whole frequency band. The LO generation block has selectable multiple division ratios of ${\div}2$, ${\div}16$, and ${\div}32$ to generate LO I/Q signals for T-DMB/DAB/FM Radio systems in L-Band (1173~1973 MHz), VHF-III (147~246 MHz), VFH-II (74~123 MHz), respectively. The measured integrated phase noise is quite low as it is lower than 0.8 degree RMS over the whole frequency band. Total locking time of the ${\Delta}{\Sigma}$ frequency synthesizer including VCO frequency calibration time is less than $50{\mu}s$. The wideband ${\Delta}{\Sigma}$ fractional-N frequency synthesizer is fabricated in $0.13{\mu}m$ CMOS technology, and it consumes 15.8 mA from 1.2 V DC supply.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07b
• /
• pp.851-856
• /
• 2003

We have investigated the material and electrical properties of $Bi_{4-x}La_xTi_3O_{12}$ (BLT) ferroelectric thin film for ferroelectric nonvolatile memory applications of capacitor type and single transistor type. The 120nm thick BLT films were deposited on $Pt/Ti/SiO_2/Si$ and $SiO_2/Nitride/SiO_2$ (ONO) substrates by the sol-gel spin coating method and were annealed at $700^{\circ}C$. It was observed that the crystallographic orientation of BLT thin films were strongly affected by the excess Bi content and the intermediate rapid thermal annealing (RTA) treatment conditions regardeless of two type substrates. However, the surface microstructure and roughness of BLT films showed dependence of two different type substrates with orientation of (111) plane and amorphous phase. As increase excess Bi content, the crystallographic orientation of the BLT films varied drastically in BLT films and exhibited well-crystallized phase. Also, the conversion of crystallographic orientation at intermediate RTA temperature of above $450^{\circ}C$ started to be observed in BLT thin films with above excess 6.5% Bi content and the rms roughness of films is decreased. We found that the electrical properties of BLT films such as the P-V hysteresis loop and leakage current were effectively modulated by the crystallographic orientations change of thin films.

• Journal of Broadcast Engineering
• /
• v.17 no.5
• /
• pp.742-755
• /
• 2012

In this paper, we propose a parallel deblocking algorithm to resolve workload imbalance when the deblocking filter of high efficiency video coding (HEVC) decoder is parallelized. In HEVC, the deblocking filter which is one of the in-loop filters conducts two-step filtering on vertical edges first and horizontal edges later. The deblocking filtering can be conducted with high-speed through data-level parallelism because there is no dependency between adjacent edges for deblocking filtering processes. However, workloads would be imbalanced among regions even though the same amount of data for each region is allocated, which causes performance loss of decoder parallelization. In this paper, we solve the problem for workload imbalance by predicting the complexity of deblocking filtering with coding unit (CU) depth information at a coding tree block (CTB) and by allocating the same amount of workload to each core. Experimental results show that the proposed method achieves average time saving (ATS) by 64.3%, compared to single core-based deblocking filtering and also achieves ATS by 6.7% on average and 13.5% on maximum, compared to the conventional uniform data-level parallelism.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.19-24
• /
• 2007

With recent advancement of high-speed, multi-gigabit data transmission capabilities, serial links have been more widely adopted in industry than parallel links. Since the parallel link design forces its transmitter to transmit both the data and the clock to the receiver at the same time, it leads to hardware's intricacy during high-speed data transmission, large power consumption, and high cost. Meanwhile, the serial links allows the transmitter to transmit data only with no synchronized clock information. For the purpose, clock and data recovery circuit becomes a very crucial key block. In this paper, a 5.4Gbps half-rate bang-bang CDR is designed for the applications of high-speed graphic DRAM interface. The CDR consists of a half-rate bang-bang phase detector, a current-mirror charge-pump, a 2nd-order loop filter, and a 4-stage differential ring-type VCO. The PD automatically retimes and demultiplexes the data, generating two 2.7Gb/s sequences. The proposed circuit is realized in 66㎚ CMOS process. With input pseudo-random bit sequences (PRBS) of $2^{13}-1$, the post-layout simulations show 10psRMS clock jitter and $40ps_{p-p}$ retimed data jitter characteristics, and also the power dissipation of 80mW from a single 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.44 no.5
• /
• pp.62-70
• /
• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• Transactions of the Korean Society of Mechanical Engineers B
• /
• v.40 no.3
• /
• pp.165-172
• /
• 2016

An experimental study of the thermal-hydraulic characteristics of passive safety systems (PSSs) was conducted using a system-integrated modular advanced reactor-integral test loop (SMART-ITL). The present passive safety injection system for the SMART-ITL consists of one train with the core makeup tank (CMT), the safety injection tank, and the automatic depressurization system. The objective of this study is to investigate the injection effect of the PSS on the small-break loss-of-coolant accident (SBLOCA) scenario for a 0.4 inch line break in the safety-injection system (SIS). The steady-state condition was maintained for 746 seconds before the break. When the major parameters of the target value and test results were compared, most of the thermal-hydraulic parameters agreed closely with each other. The water level of the reactor pressure vessel (RPV) was maintained higher than that of the fuel assembly plate during the transient, for the present CMT and safety injection tank (SIT) flow rate conditions. It can be seen that the capability of an emergency core cooling system is sufficient during the transient with SMART passive SISs.