• Journal of Sensor Science and Technology
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• v.32 no.5
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• pp.328-333
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• 2023

This study experimentally verified the etch rate of the SiO₂ sacrificial layer etching process with a single etch hole using vapor-phase hydrogen fluoride (VHF) etching. To fabricate small-sized polysilicon etch holes, both circular and triangular pattern masks were employed. Etch holes were fabricated in the polysilicon thin film on the SiO₂ sacrificial layer, and VHF etching was performed to release the polysilicon thin film. The lateral etch rate was measured for varying etch hole sizes and sacrificial layer thicknesses. Based on the measured results, we obtained an approximate equation for the etch rate as a function of the etch hole size and sacrificial layer thickness. The etch rates obtained in this study can be utilized to minimize structural damage caused by incomplete or excessive etching in sacrificial layer processes. In addition, the results of this study provide insights for optimizing sacrificial layer etching and properly designing the size and spacing of the etch holes. In the future, further research will be conducted to explore the formation of structures using chemical vapor deposition (CVD) processes to simultaneously seal etch hole and prevent adhesion owing to polysilicon film vibration.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1924-1926
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• 2001

A novel wet release process ($\mu$ CARP - Micro Channel Assisted Release Process) for releasing an extreme large-area plate structure without etching hole is proposed and experimented. Etching holes in conventional process reduce a effective area and degrade an optical characteristics by a diffraction. In addition, as the area of a released structure increases, the stietion becomes more serious. The proposed process resolves these problems by the introduction of a micro fluidic channel beneath the structure which will be released. In this paper, a 5 mm${\times}$5mm-single crystal silicon plate structure was released by the proposed $\mu$CARP without etch holes on the structure. The variation in etching time with respect to the of the introduced micro channel is also examined. This process is expected to be beneficial for the actuator of a nano-scale data storage and the scanning mirror.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.4 no.1
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• pp.83-91
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• 1994

We have constructed a vertical gradient freeze (VGF) grower for GaAs single crystals 2 inch in diameter and have grown semi-insulating GaAs co-doped with Cr and In. For the co-doped crystal, the segregation coefficients of the dopants remain unchanged when compared to those doped with only Cr or In. The concentration of Cr and in atoms range from about $2{\Times}10_{16} to 3{imes}10^{17} cm^{-3}$ and $2{\Times}10^{19} to 3{\Times}10^{20} cm^{-3}$ at the seed to the tail part of the grown crystal, respectively. The averaged dislocation etch pit density is found to be less than $8000 cm^{-2}$ throughout the ingot. It is also found that there is some evidence of lattice hardening for the crystal in which the dislocation density is decreased to less than $1000 cm^{-2}$ as In concentration increases. The resistivity increases abruptly from $10^{-2}$ up to $10^8$ Ohm-cm, while the carrier concentration decreases from $10^{16}$ to $10^8 cm^{-3}$ along the growth direction of the GaAs crystal. Semi-insulating properties can be obtained above a critical concentration of Cr of about $6{\Times}10{^16} cm^{-3}$ in the crystal. The main deep levels existing in the GaAs: Cr,In sample are two electron traps at $E_C-0.81eV, E_C-0.35eV$, and two hole traps at $E_V+0.89eV, E_V+0.65eV$.