• 한국전기전자재료학회논문지
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• 제18권11호
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• pp.1048-1055
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• 2005

The formula to calculate a variation of optical path length of single crystal by the electric field was derived by this study. The formula was applied to $Bi_{12}SiO_{20}$ single crystal. The results are as follows. In case of the applied electric field in the body diagonal direction and the passing light along the same direction, the variation of optical path length had the largest value. The symmetry of the space distribution of optical path length satisfied $E3C_2\;8C_3$, the set of elements of the symmetry of $Bi_{12}SiO_{20}$ single crystal. The property which gave the largest influence to the variation of optical path length is the strain of length by the Inverse piezoelectric effect. The second influence, is the variation of the refractive index by the electro-optic effect. The variation of optical path length by the inverse piezoelectric effect and by the electro-optic effect have a reverse sign each other.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집
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• pp.1-6
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• 2004

In this paper author describe the undoped and $Co^{2+}$ (0.5mole%)doped $Cd_4GeS_6$ single crystals were grown by the chemical transporting reaction(CTR) method using high purity(6N) Cd, $GeS_2$, S elements. It was found from the analysis of X-ray diffraction that the undoped and $Co^{2+}$(0.5mole%) doped $Cd_{4}GeS_{6}$ compounds have a monoclinic structure in space grop Cc. The optical energy band gap was direct band gap and temperature dependence of optical energy gap was fitted well to Varshni equation. Impurity optical absorption peaks due to the doped cobalt in the $Cd_4GeS_6:Co^{2+}$ single crystal were observed at 3593cm-1, 5048cm-1, 5901cm-1, 7322cm-1, 12834cm-1, 13250cm-1, 14250cm-1，and 14975cm-1 at 11.3K.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 영호남 합동 학술대회 및 춘계학술대회 논문집 센서 박막 기술교육
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• pp.27-30
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• 2006

In this paper, the undoped and Co-doped $Zn_4SnSe_6$ single crystals grown by the chemical transporting reaction(CTR) method using iodine as a transporting agent are investigated. For the crystal growth, the temperature gradient of the CTR furnace was kept at $680^{\circ}C$ for the source zone and at $780^{\circ}C$ for the growth zone for 7days. It was found from the analysis of x-ray diffraction that the $Zn_4SnSe_6$ and $Zn_4SnSe_6Co^{2+}$ compounds have a monoclinic structure. The direct optical energy band gap of the $Zn_4SnSe_6$ and $Zn_4SnSe_6Co^{2+}$ single crystals at 300K were found to be 2.146eV and 2.042eV.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 춘계학술대회 논문집
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• pp.67-70
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• 1998

In this work, the freestanding GaN single crystalline substrates without cracks were grown by hydride vapor phase epitaxy (HVPE). The GaN substrates, having a current maximum size of 350 $\mu\textrm{m}$-thickness and 10${\times}$10 $\textrm{mm}^2$ area, were obtained by HVPE growth GaN on sapphire substrate and subsequent mechanical removal of the sapphire substrate. A lattice constant of c$\_$0/=5.18486 ${\AA}$ and a FWHM of DCXRD was 650 arcsec for the single crystalline freestanding GaN substrate. The low temperature PL spectrum consist of excitonic emission and deep donor to acceptor pair recombination at 1.8 eV. The Raman E$_2$ (high) mode frequency was 567 cm$\^$-1/ which was the same as that of strain free bulk single crystals. The Hall mobility and carrier concentration was 283 $\textrm{cm}^2$/V$.$sec and 1.1${\times}$10$\^$18/ cm$\^$-3/, respectively. The freestanding and crack-free GaN single crystalline substrate suitable for the homoepitaxial growth of GaN, and the HVPE method are promising approaches for the preparation of large area, crack-free GaN substrates.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.

• 한국전기전자재료학회논문지
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• 제20권6호
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• pp.546-549
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• 2007

As a rule, high temperature superconducting coated conductors have multi-layered buffers consisting of seed, diffusion barrier and cap layers. Multi-buffer layer deposition requires longer fabrication time. This is one of main reasons which increases fabrication cost. Thus, single buffer layer deposition seems to be important for practical coated conductor process. In this study, a single layered buffer deposition of $CeO_2$ for low cost coated conductors has been tried using thermal evaporation technique. 100 nm-thick $CeO_2$ layers deposited by thermal evaporation were found to act as a diffusion layer. $1\;{\mu}m-thick$ SmBCO superconducting layers were deposited by thermal co-evaporation on the $CeO_2$ buffered Ni-5%W substrate. Critical current of 90 A/cm was obtained for the SmBCO coated conductors.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.240-241
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• 2007

In general, high temperature superconducting coated conductors have intermediary buffers layer consisting of seed, diffusion barrier and cap layers. Simplification of the oxide materials buffer architecture in the fabrication of high temperature superconducting coated conductors is required because the deposition of multi-layers buffer architecture leads to a longer manufacturing time and a higher cost process of coated conductors. Thus, single buffer layer deposition seems to be important for practical coated conductor manufacturing process. In this study, a single gradient layered buffer deposition process of YZO for low cost coated conductors has been tried using DC reactive sputtering technique. About several thick YZO gradient single buffer layers deposited by DC co-sputtering process were found to act as a diffusion layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.381-384
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• 2004

The stochiometric nix of evaporating materials for the $AgInS_2$ single crystal thin films were prepared from horizontal furnace. The polycrystal structure obtaind from the power x-ray diffraction was chalcopyrite. The lattice costants $a_0\;and\;c_0$ were $a_0=5.86(5.82)\;A,\;c_0=11.355(11.17)\;A$. To obtains the single crystal thin films, $AgInS_2$ mixed crystal were deposited on throughly etched GaAs(100) by the Hot Wall Epitaxy(HWE) system. The temperates of the source and the substrate were $590^{\circ}C\;and\;450^{\circ}C$, respectively. The crystalline structure of single crystal thin films was investigated by the double crystal X-ray diffraction(DCXD). Hall effect on this sample was measured by the method of van der Pauw and studied on carrier density and mobility dependence on temperature. In order to explore the applicability as a photoconductive cell, we measured the sensitivity($\gamma$), the ratio of photocurrent to dark current (pc/dc), maximum allowable power dissipation(MAPD), spectral response and response time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.461-462
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• 2006

A single-gap and single-gamma transflective liquid-crystal (LC) display using patterned vertical alignment (PVA) mode was designed. In the device, a vertical electric field drives a vertically aligned LC to tilt down to optimize polarization efficiency. Electrodes of transmissive and reflective area were patterned $22.5^{\circ}$ and $45^{\circ}$ with respect to the polarizer so that a tilt-down direction of the LC director was $22.5^{\circ}$ and $45^{\circ}$ in the reflective and transmissive regions, respectively. In the device, the cell gap was the same for both regions, and the gamma curve matched each other in both regions because tilt angle of LC director was the same according to the applied voltage. Moreover, the dark state was irrespective of the cell retardation value at normal direction, which was highly important in massive fabrications. The switching principle and electro-optic characteristics of the device are reported herein.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.180-181
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• 2006

CdSe single crystal was grown by sublimation method in the two-step vertical electric furnace. This CdSe single crustal had hexagonal structure whose lattice constants of $a_0$ and $c_0$ were measured $4.299\;{\AA}$ and $7.009\;{\AA}$ by extrapolation method, respectively. CdSe single crystal was n-type semiconductor values were measured from Hall data by Van der Pauw method in the room temperature. Mobility tends to increase in proportion to $T^{3/2}$ from 33K to 130K due to impurity scattering. but mobility tends to decrease in proprtion to $T^{-3/2}$ from 130K to 293K due to lattice scattering. CdSe thin film was made by electron beam evaporation technique had also hexagonal structure. The grain size of this thin film was grown to $1{\mu}m$ as a result of annealing in the vapor of Ar or Cd. Annealde CdSe thin film was n-type semiconductor whose carrier density had about $7{\times}10^{12}cm^{-3}$ and its mobility had about $1.6{\times}10^3cm^2/V$ sec at room temperature.