• 한국전기전자재료학회논문지
• /
• 제16권4호
• /
• pp.292-297
• /
• 2003

We fabricated a single crystal silicon thin film transistor for active matrix organic light emitting displays(AMOLEDs) using silicon on insulator wafer (SOI wafer). Poly crystal silicon thin film transistor(poly-Si TFT) Is actively researched and developed nowsdays for a pixel switching devices of AMOLEDs. However, poly-Si TFT has some disadvantages such as high off-state leakage currents and low field-effect mobility due to a trap of grain boundary in active channel. While single crystal silicon TFT has many advantages such as high field effect mobility, low off-state leakage currents, low power consumption because of the low threshold voltage and simultaneous integration of driving ICs on a substrate. In our experiment, we compared the property of poly-Si TFT with that of SOI TFT. Poly-Si TFT exhibited a field effect mobility of 34 $\textrm{cm}^2$/Vs, an off-state leakage current of about l${\times}$10$\^$-9/ A at the gate voltage of 10 V, a subthreshold slope of 0.5 V/dec and on/off ratio of 10$\^$-4/, a threshold voltage of 7.8 V. Otherwise, single crystal silicon TFT on SOI wafer exhibited a field effect mobility of 750 $\textrm{cm}^2$/Vs, an off-state leakage current of about 1${\times}$10$\^$-10/ A at the gate voltage of 10 V, a subthreshold slope of 0.59 V/dec and on/off ratio of 10$\^$7/, a threshold voltage of 6.75 V. So, we observed that the properties of single crystal silicon TFT using SOI wafer are better than those of Poly Si TFT. For the pixel driver in AMOLEDs, the best suitable pixel driver is single crystal silicon TFT using SOI wafer.

• 한국전기전자재료학회논문지
• /
• 제16권12S호
• /
• pp.1237-1241
• /
• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• 반도체디스플레이기술학회지
• /
• 제2권2호
• /
• pp.9-15
• /
• 2003

This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12" silicon wafer for spin etcher. Halogen lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and adaptive filtering. Test wafers with three kinds of priori-known films, polysilicon(300 nm), silicon-oxide(500 nm) and silicon-oxide(600 nm), are measured while the wafer is spinning at 20 Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 0.8% error.rror.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2008년도 추계학술대회 논문집
• /
• pp.747-748
• /
• 2008

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2011년도 춘계학술대회 논문집
• /
• pp.863-864
• /
• 2011

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2008년도 추계학술대회 논문집
• /
• pp.749-750
• /
• 2008

• 반도체디스플레이기술학회지
• /
• 제9권2호
• /
• pp.21-25
• /
• 2010

In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

• 한국태양에너지학회 논문집
• /
• 제32권spc3호
• /
• pp.194-198
• /
• 2012

Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 80% of the market, despite the development of various thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon materials remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner the silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials with different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With less amount of paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 120 micron thickness of the wafer even though the conversion efficiency decrease by 0.5% occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al layer application.

• 한국태양에너지학회:학술대회논문집
• /
• 한국태양에너지학회 2011년도 춘계학술발표대회 논문집
• /
• pp.101-104
• /
• 2011

Many studies in crystalline silicon solar cell fabrication have been focused on high efficiency and low cost. In this paper, we carried out the doping procedure by varying the silicon wafer thicknesses and sheet resistance. The silicon wafers with various thicknesses were obtained by shiny etching and texturing. The thicknesses of wafers were 100, 120, 150, and $180{\mu}m$. The emitter layer formed by $POCl_3$ doping process had sheet resistance with 40 and $80{\Omega}/sq$ for selective emitter application. This experiment indicated wafer thickness did not influence sheet resistance but lifetime was strongly effected.

• Mass Spectrometry Letters
• /
• 제12권1호
• /
• pp.26-30
• /
• 2021

The impurity concentration is a crucial parameter for semiconductor thin films. Evaluating the impurity distribution in silicon thin film is another challenge. In this study, we have investigated the doping concentration of boron in silicon thin film using time of flight secondary ion mass spectrometry in dynamic mode of operation. Boron doped silicon film was grown on i) p-type silicon wafer and ii) borosilicate glass using hot wire chemical vapor deposition technique for possible applications in optoelectronic devices. Using well-tuned SIMS measurement recipe, we have detected the boron counts 101~104 along with the silicon matrix element. The secondary ion beam sputtering area, sputtering duration and mass analyser analysing duration were used as key variables for the tuning of the recipe. The quantitative analysis of counts to concentration conversion was done following standard relative sensitivity factor. The concentration of boron in silicon was determined 1017~1021 atoms/㎤. The technique will be useful for evaluating distributions of various dopants (arsenic, phosphorous, bismuth etc.) in silicon thin film efficiently.