• Journal of the Korean Vacuum Society
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• 제6권3호
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• pp.242-248
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• 1997

Porous silicons were prepared by dry etching as well as by chemical etching. The latter is a conventional method used by many researchers. Meanwhile, the former is a new method we developed. Also the porous silicon structure was made by E-beam lithography technique. However, due to the limit of this technique, minimum size we could produce was about 0.3 $\mu\textrm{m}$ in diameter on silicon wafer. In a new method, the porous silicon microstructure was fabricated by using Reactive Ion Etching method after covering with diamond powder on 4 inch wafer by using spin coater. In this method, diamond powder acted as a mask. The morphology of samples prepared under many different conditions were analysed be SEM and AFM. And we measured PL spectra for the samples. Based on these results, we observed the structure of a few hundreds $\AA$ in size from porous silicon which was made by dry etching with diamond powder. Also the PL peak for these samples lied around 590 nm compared to 760 nm for chemically etched porous silicon.

• Journal of Sensor Science and Technology
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• 제19권2호
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• pp.137-141
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• 2010

In this paper, we fabricated silicon piezoresistive pressure sensor with dry etching technology which used Deep-RIE and etching delay technology which used SOI(silicon-on-insulator) wafer. We improved pressure sensor offset and its temperature dependence by removing oxidation layer of SOI wafer which was used for dry etching delay layer. Sensitivity of the fabricated pressure sensor was about 0.56 mV/V${\cdot}$kPa at 10 kPa full-scale, and nonlinearity of the fabricated pressure sensor was less than 2 %F.S. The zero off-set change rate was less than 0.6 %F.S.

• Journal of the Korean Ceramic Society
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• 제39권6호
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• pp.570-575
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• 2002

The present tendency of electrical and electronics is concentrated on MEMS devices for advantage of miniaturization, intergration, low electric power and low cost. Therefore it is essential that high aspect ratio and high etch rate by HDP technology development, so that silicon deep trench etching reactions was studied by ICP equipment. Deep trench etching of silicon was investigated as function of platen power, etch step time of etch/passivation cycle time and SF$\_$6/:C$_4$F$\_$8/ flow rate. Their effects on etch profile, scallops, etch rate, uniformity and selectivity were also studied.

• The Transactions of the Korean Institute of Electrical Engineers C
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• 제53권2호
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• pp.62-66
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• 2004

This paper investigated the characteristics of a newly developed high density hollow cathode plasma (HCP) system and its application for the etching of silicon wafers. We used SF$_{6}$ and $O_2$ gases in the HCP dry etch process. Silicon etch rate of $0.5\mu\textrm{m}$/min was achieved with $SF_6$$O_2$plasma conditions having a total gas pressure of 50mTorr, and RF power of 100 W. This paper presents surface etching characteristics on a crystalline silicon wafer and large area cast type multicrystlline silicon wafer. The results of this experiment can be used for various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications.s.

• Journal of Sensor Science and Technology
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• 제16권2호
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• pp.126-131
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• 2007

In this paper, we fabricated piezoresistive pressure sensor with dry etching technology which used ICP-RIE (inductively coupled plasma reactive ion etching) and etching delay technology which used SOI (silicon-on-insulator). Structure of the fabricated pressure sensor shows a square diaphragm connected to a frame which was vertically fabricated by dry etching process and a single-element four-terminal gauge arranged at diaphragm edge. Sensitivity of the fabricated sensor was about 3.5 mV/V kPa at 1 kPa full-scale. Measurable resolution of the sensor was not exceeding 20 Pa. The nonlinearity of the fabricated pressure sensor was less than 0.5 %F.S.O. at 1 kPa full-scale.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.418-418
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• 2008

The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

• Journal of Information Display
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• 제2권4호
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• pp.1-7
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• 2001

This paper investigates the characteristics of a newly developed high density hollow cathode plasma(HCP) system and its application for the etching of silicon wafers. We used $SF_6$ and $O_2$ gases in the HCP dry etch process. This paper demonstrates very high plasma density of $2{\times}10^{12}cm^{-3}$ at a discharge current of 20 rna, Silicon etch rate of 1.3 ${\mu}m$/min was achieved with $SF_6/O_2$ plasma conditions of total gas pressure of 50 mTorr, gas flow rate of 40 seem, and RF power of200W. This paper presents surface etching characteristics on a crystalline silicon wafer and large area cast type multicrystlline silicon wafer. We obtained field emitter tips size of less than 0.1 ${\mu}m$ without any photomask step as well as with a conventional photolithography. Our experimental results can be applied to various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications. In this research, we studied silicon etching properties by using the hollow cathode plasma system.

• Journal of Electrical Engineering and Technology
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• 제7권3호
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• pp.396-400
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• 2012

Novel fabrication method of nanobridge array of various materials was proposed using suspended silicon nanowire array as a sacrificial template structure. Nanobridges of various materials can be simply fabricated by direct deposition with thermal evaporation on the top of prefabricated suspended silicon nanobridge arrays, which are used as a sacrificial structure. Since silicon nanowire can be easily removed by selective dry etching, nanobridge arrays of an intended material are finally obtained. In this paper, metal nanobridges of Ti/Au, around 50-200 nm in thickness and width, 5-20 ${\mu}m$ in length were fabricated to prove the advantages of the proposed nanowire or nanobridge fabrication method. The nanobridges of Ti/Au after complete removal of sacrificial silicon nanowire template were well-established and bending of nanobridge caused by the tensile stress was observed after silicon removing. Up to 50 nm and 10 ${\mu}m$ of silicon nanowire in diameter and length respectively was also very useful for nanowire templates.

• Korean Journal of Materials Research
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• 제20권12호
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• pp.649-653
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• 2010

In this paper, double texturization of multi crystalline silicon solar cells was studied with laser and reactive ion etching (RIE). In the case of multi crystalline silicon wafers, chemical etching has problems in producing a uniform surface texture. Thus various etching methods such as laser and dry texturization have been studied for multi crystalline silicon wafers. In this study, laser texturization with an Nd:$YVO_4$ green laser was performed first to get the proper hole spacing and $300{\mu}m$ was found to be the most proper value. Laser texturization on crystalline silicon wafers was followed by damage removal in acid solution and RIE to achieve double texturization. This study showed that double texturization on multi crystalline silicon wafers with laser firing and RIE resulted in lower reflectance, higher quantum yield and better efficiency than that process without RIE. However, RIE formed sharp structures on the silicon wafer surfaces, which resulted in 0.8% decrease of fill factor at solar cell characterization. While chemical etching makes it difficult to obtain a uniform surface texture for multi crystalline silicon solar cells, the process of double texturization with laser and RIE yields a uniform surface structure, diminished reflectance, and improved efficiency. This finding lays the foundation for the study of low-cost, high efficiency multi crystalline silicon solar cells.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제18권12호
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• pp.1075-1079
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• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.