• 한국결정성장학회지
• /
• 제11권3호
• /
• pp.89-95
• /
• 2001

규소 결정의 용융 온도 근처인 $1350^{\circ}C$에서 Ar과 $O_{2}$gas를 이용하여 규소 wafer의 열처리시 vacancy ty[e 결함의 거동에 대해 알아보았다. 이 열처리에서는 wafer의 표면보다 wafer내부에서 결함의 용해속도가 매우 높음을 확인하였다. 이는 $1350^{\circ}C$에서는 규소내의 평형산소농도가 대부분의 CZ silicon에서의 산소농도보다 높아 산소의 understaturation현상과 silicon interstitial농도의 영향에 기인된 것으로 예상된다. 열처리 분위기의 영향을 알아보기 위하여 Ar과 $O_{2}$ 분위기에서 열처리한 결과 vacancy type 결함의 용해속도는 wafer의 내부에서는 차이가 없었고, wafer의 표면에서는 Ar이 $O_{2}$의 경우보다 결함의 용해속도가 높았다. $O_{2}$의 경우에는 표면산화막 성장시 유입된 silicon interstitial의 농도가 높아 결함의 용해속도가 떨어지는 것으로 판단된다. 이는 기존 연구에서 예상된 silicon interstitial이 vacancy cluster로 알려진 결정결함의 제거에 기여한다는 예상과는 상반된다. 본 연구의 결과 silicon interstitial의 존재는 void외부 산화막의 용해속도를 늦추어 결함 용해속도를 떨어뜨리는 것으로 예상된다.

• Transactions on Electrical and Electronic Materials
• /
• 제5권4호
• /
• pp.143-147
• /
• 2004

Surface defects and bulk defects on SOI wafers are studied. Two new metrologies have been proposed to characterize surface and bulk defects in epitaxial layer transfer (ELTRAN) wafers. They included the following: i) laser scattering particle counter and coordinated atomic force microscopy (AFM) and Cu-decoration for defect isolation and ii) cross-sectional transmission electron microscope (TEM) foil preparation using focused ion beam (FIB) and TEM investigation for defect morphology observation. The size of defect is 7.29 urn by AFM analysis, the density of defect is 0.36 /cm$^2$ at as-direct surface oxide defect (DSOD), 2.52 /cm$^2$ at ox-DSOD. A hole was formed locally without either the silicon or the buried oxide layer (Square Defect) in surface defect. Most of surface defects in ELTRAN wafers originate from particle on the porous silicon.

• 한국결정성장학회지
• /
• 제15권2호
• /
• pp.45-50
• /
• 2005

규소 표면의 기계적 손상은 산화 공정 중에 규소 표면에 여러 가지 형태의 결함들을 발생 시킨다. 규소 표면에 손상을 주는 마모 입자가 커짐에 따라 OISF보다는 etch pit의 형상이 동굴형인 선 결함(line defects)들이 많이 발생된다. 이들 결함들은 실리콘 결정을 성장시키는 단계에서 형성되는 결함들과는 상호 관련이 없다. 방향성 응고법으로 성장된 규소 결정속에 존재하는 결함들은 주로 twin과 stacking fault들이며 응고과정에서 발생이 예상되는 응력에 의한 전위는 거의 발견되지 않았다. 따라서 Czochralski 법으로 성장된 단 결정 규소뿐 아니라 방향성 응고법으로 성장된 다 결정 규소 기판도 표면의 결함들을 이용하여 extrinsic gettering을 통한 규소 결정 내부의 불순물 제거의 가능성이 높다.

• 한국표면공학회지
• /
• 제31권5호
• /
• pp.237-244
• /
• 1998

In this stydy, submicron shallow trenches applied to STI(shallow tench isolation) were etched using inductively coupled $CI_2$/HBr and $CI_2/N_2$plasmas and the physical and electrical defects remaining on the etched silicon trench surfaces and the effects of various annealing and oxidation on the removal of the defects were studied. Using high resolution electron microscopy(HRTEM), Physical defects were investigated on the silicon trench surfaces etched in both 90%$CI_2$/ 10%$N_2$ and 50%$CI_2$/50%HBr. Among the areas in the tench such as trench bottom, bottom edge, and sidewall, the most dense defects were found near the trench bottom edge, and the least dense defects were found near the trench bottom edge, and least dense defects compared to that etched with ment as well as hydrogen permeation. Thermal oxidation of 200$\AA$ atthe temperature up to $1100^{\circ}C$apprars not to remove the defects formed on the etched silicon trenches for both of the etch conditions. To remove the physicall defects, an annealing treatment at the temperature high than $1000^{\circ}C$ in N for30minutes was required. Electrical defects measured using a capacitance-voltage technique showed the reduction of the defects with increasing annealing temperature, and the trends were similar to the results on the physical defects obtained using transmission electron microscopy.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2005년도 춘계학술대회 논문집
• /
• pp.1083-1086
• /
• 2005

Light scattering measurement system that can evaluate light scattering characteristic from defects on silicon wafer surface has been developed. The system uses $Ar^+$ laser as an illumination source, and a highly sensitive photomultiplier tube (PMT) for detecting scattered light from defects. Unlike with conventional measurement system, our system has ability to measure scattered light pattern from wide range of scattering angles with changeable incidence condition. It is shown that our developed system is effective to discriminate the types and sizes of defects from basic experimental results using a microscatch and a PSL sphere.

• Applied Science and Convergence Technology
• /
• 제23권3호
• /
• pp.113-127
• /
• 2014

For more than five decades, silicon has dominated the semiconductor industry that supports memory devices, ICs, photovoltaic devices, etc. Photoluminescence (PL) is an attractive silicon characterization technique because it is contactless and provides information on bulk impurities, defects, surface states, optical properties, and doping concentration. It can provide high resolution spectra, generally with the sample at low temperature and room-temperature spectra. The photoluminescence properties of silicon at low temperature are reviewed and discussed in this study. In this paper, silicon bulk PL spectra are shown in multiple peak positions at low temperature. They correspond with various impurities such as In, Al, and Be, phonon interactions, for example, acoustical phonons and optical phonons, different exciton binding energies for boron and phosphorus, dislocation related PL emission peak lines, and oxygen related thermal donor PL emissions.

• 한국재료학회지
• /
• 제22권1호
• /
• pp.8-15
• /
• 2012

Silicon-based thin film was prepared at room temperature by an electrochemical deposition method and a feasibility study was conducted for its use as an anode material in a rechargeable lithium battery. The growth of the electrodeposits was mainly concentrated on the surface defects of the Cu substrate while that growth was trivial on the defect-free surface region. Intentional formation of random defects on the substrate by chemical etching led to uniform formation of deposits throughout the surface. The morphology of the electrodeposits reflected first the roughened surface of the substrate, but it became flattened as the deposition time increased, due primarily to the concentration of reduction current on the convex region of the deposits. The electrodeposits proved to be amorphous and to contain chlorine and carbon, together with silicon, indicating that the electrolyte is captured in the deposits during the fabrication process. The silicon in the deposits readily reacted with lithium, but thick deposits resulted in significant reaction overvoltage. The charge efficiency of oxidation (lithiation) to reduction (delithiation) was higher in the relatively thick deposit. This abnormal behavior needs to clarified in view of the thickness dependence of the internal residual stress and the relaxation tendency of the reaction-induced stress due to the porous structure of the deposits and the deposit components other than silicon.

• 한국결정성장학회지
• /
• 제16권2호
• /
• pp.66-70
• /
• 2006

실리콘웨이퍼 표면에 기계적인 손상을 가한 후 산화 열처리 공정을 실시하면 온도와 기계적인 손상의 크기에 따라 여러 가지 결정 결함이 발생된다. 기계적인 손상이 크고 열처리 온도가 증가함에 따라 dislocation loop 등의 대형 결함들이 발생되고 열처리 온도가 낮거나 손상의 크기가 작을수록 OISF(Oxidation Induced Stacking Faults)등의 소형 결함들이 많이 발생된다. Minority carrier lifetime을 측정하여본 결과 결함의 크기가 작을수록 minority carrier lifetime이 높은 것으로 밝혀졌다. 더욱이 dislocation loop 등의 결정 결함보다는 결함 발생 이전 단계인 strained layer등이 금속불순물에 대한 gettering의 효과가 더욱 높음을 알 수 있었다.

• 반도체디스플레이기술학회지
• /
• 제17권4호
• /
• pp.1-5
• /
• 2018

Atomic force microscopy (AFM) simulation for Si (001) surface defects was conducted by using density functional theory (DFT). Three major defects on the Si (001) surface are difficult to analyze due to external noises that are always present in the images obtained by AFM. Noise-free surface defects obtained by simulation can help identify the real surface defects on AFM images. The surface defects were first optimized by using a DFT code. The AFM tip was designed by using five carbon atoms and positioned on the surface to calculate the system's energy. Forces between tip and surface were calculated from the energy data and converted into an AFM image. The simulated AFM images are noise-free and, therefore, can help evaluate the real surface defects present on the measured AFM images.

• 한국표면공학회지
• /
• 제28권3호
• /
• pp.174-181
• /
• 1995

Multilayered silicon cantilever beams as interconnection systems for bare chip burn-in socket applications have been designed, fabricated and characterized. Fabrication processes of the beam are employing standard semiconductor processes such as thin film processes and epitaxial layer growth and silicon wet etching techniques. We investigated silicon etch rate in 1-3-10 etchant as functions of doping concentration, surface mechanical stress and crystal defects. The experimental results indicate that silicon etch rate in 1-3-10 etchant is strong functions of doping concentration and crystal defect density rather than surface mechanical stress. We suggested the new fabrication processes of multilayered silicon cantilever beams.