• 대한전기학회논문지
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• 제43권6호
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• pp.1036-1038
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• 1994

In this paper, a silicon piezoresistive accelerometer is designed and fabricated using a silicon direct bonded wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW as an etchant. The measured sensitivity and the resonant frequency are 0.02 mV/V.g and 3.4 kHz, respectively. The nonlinearity is less than $\pm$0.3% of the full scale of the output.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권3호
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• pp.124-132
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• 2000

In this paper, presented are an active surface-micromachined silicon accelerometer, force rebalance loop using parametric robust control method, and experimental results with a real micromachined accelerometer. And finally, a robust controller of the form of PID compensator was designed to construct force rebalance loop. Through the frequency response analysis, it is shown that the loop guarantees appropriate stability and robustness. Experiments with a real accelerometer demonstrated that the proposed loop effectively controls the position of the accelerometer's proof mass. It also demonstrated that the resolution of the fabricated accelerometer is better than 1mg. Compared with a commercial accelerometer the proposed force rebalance silicon accelerometer showed better performances.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.56-60
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• 1996

This paper presents the initial results of development of a inertial navigation grade silicon pendulous accelerometer. This effort focused on developing a bulk-micromachined silicon pendulum and designing a PI-servo controller. Performance data presented in this paper includes threshold, bias short term stability and nonlinearity of scale factor. This accelerometer developed is demonstrated the feasibility of meeting one-nautical-mile-per-hour accuracy.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 G
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• pp.2504-2508
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• 1998

In this paper, we propose the new detecting method for three dimensional piezoresistive silicon accelerometer. Furthermore the accelerometer is formed to have endurance for high temperature by perfect isolation of the piezoresistors using Silicon On Insulator(SOI) wafer. Sensor size are optimized with analytical formulae and extended with FEM simulation for the more detailed results. The accelerometer was fabricated by bulk micromachining techonology. We measured the temperature characteristics and the output characteristics, and the both characteristics were compared with the simulated results

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 추계학술대회 논문집
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• pp.257-258
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• 2007

• 한국광학회:학술대회논문집
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• 한국광학회 2003년도 제14회 정기총회 및 03년 동계학술발표회
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• pp.322-323
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• 2003

Silicon substrate was fabricated by bulk silicon micromachining and it's structure is based on a proof mass suspended by two beam. To monitor the acceleration, dynamic excitation of accelerometer was performed using a shaker. The attached FFPI and suspension beam are bent because support beam move with variation of the proof mass. Thus phase difference detected by the acceleration change. So we can know that resonance frequency of fabricated accelerometer is about 557 Hz and dynamic range was measured from 0 g to 2 g.

• 센서학회지
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• 제13권6호
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• pp.430-435
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• 2004

The resolution of the accelerometer, fabricated with MEMS technology is mainly affected by mechanical and electrical noise. To reduce mechanical noise, we have to increase mass of the structure part and quality factor related with the degree of vacuum packaging. On the other hand, to increase mass of the structure part, the thickness of the structure must be increased and ICP-RIE is used to fabricate the high aspect ratio structure. At this time, footing effect make the sensitivity of the accelerometer decreasing. This paper presents a hybrid SOG(Silicon On Glass) Process to fabricate a lateral silicon accelerometer with differential capacitance sensing scheme which has been designed and simulated. Using hybrid SOG Process, we could make it a real to increase the structural thickness and to prevent the footing effect by deposition of metal layer at the bottom of the structure. Moreover, we bonded glass wafer to structure wafer anodically, so we could realize the vacuum packaging at wafer level. Through this way, we could have an idea of controlling of quality factor.

• 전자공학회논문지D
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• 제34D권7호
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• pp.30-36
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• 1997

Bump bonded piezoesistive silicon accelerometer was fabricated by the porous silicon micromachining and th eprocess technique of integrated circuit. The output voltage of the accelerometer fabricated on (111)-oreiented Si substrates with n/n$^{+}$n triple layers showed good linear characteristic of less than 1%. The measured sensitivity and the resonant frequency was about 743 .mu.V/g and 2.04 kHz, respectively. And the transverse sensitivity of 5.2% was measured from the accelerometer. Also, to investigate an influence on the output characteristics of the sensor due to bump bonding, the values of the piezoresistors were measured through thermal-cycling test in the temperature variation form -50 to 120.deg. C. Then, there was 0.014% resistance changes about 3.61 k.ohm., so sthe output charcteristics of the sensor was less affected by bump bonding.g.

• 한국기계기술학회지
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• 제13권4호
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• pp.93-99
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• 2011

This paper presents a new type of optical silicon accelerometer using deep reactive ion etching (DRIE) and micro-stereolithography technology. Optical silicon accelerometer is based on a mass suspended by four vertical beams. A vertical shutter at the end of the mass can only moves along the sensing axis in the optical path between two single-mode optical fibers. The shutter modulates intensity of light from a laser diode reaching a photo detector. With the DRIE technique for (100) silicon, it is possible to etch a vertical shutter and beam. This ensures low sensitivity to accelerations that are not along the sensing axis. The microstructure for sensor packaging and optical fiber fixing was fabricated using micro stereolithography technology. Designed sensors are two types and each resonant frequency is about 15 kHz and 5 kHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 정기총회 및 추계학술대회 논문집 학회본부
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• pp.192-194
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• 1993

In this paper, a silicon piezoresistive accelerometer of which the cantilevers have uniform thickness is designed and fabricated with SOI wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW etchant. The fabrication processes are that of the frontside processes including the etching of the cantilevers and the doubleside alignment holes, the diffusion of the piezoresisters and patterning of the contact windows, and the metal connection process, and that of the backside processes including the etching of the shallow cavity and the seismic mass. Because of the uniformity of thickness, the performance of the accelerometer fabricated with SOI wafer is expected to be better than that of accelerometer fabricated by the time-controlled etching method.