• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.605-613
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• 1994

In this paper, we evaluate performance of multiple access for distributed wireless communication network by CSMA protocol. It is envident that the existence of hidden node in an environment degrades the performance of CSMA. In order to improve performance due to the problem of hidden node, the previous paper used random multiple access protocols a as such as ISMA, BTMA, BCMA. In this paper, We propose a protocol that we can improve performance by allowing node to sense the carrier of any other transmission on the channel in the distributed wireless communication networks The probability of transmission success was obtained by steady stats analysis under given assumptions. We confirmed that hidden node problem be virtually elimated by using a new protocol.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.507-511
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• 2010

Digital Radio Frequency Memory (below, DRFM) performs RF signal data store, delay and re-transmission. DRFM is wildly used as core module of Jammer, EW simulator, Target Echo Generator etc. This paper suggests a hardware design of DRFM which is composed RF section(RF Input/Output Module, Local Oscillator Module) and Digital section(ADC module, memory, DAC module), and confirm the validity of the propose by the test result.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.504-505
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• 2014

In this paper, by using hardware in the loop(HIL) of the EES, which is an inverter of high-rated technique and analyze the function. By exchanging information between the simulation and system controller to be used in a live system, HIL approach, approach experimental is used to interpret the system mass analysis is not possible in a real system some. This paper presents the implementation of the EES and the RTDS DSP28335 is a real-time connection to the electrical signal, and to verify the actual system is difficult, it was possible to analyze the performance of the system. Thus, it is expected to contribute I raise the stability and reliability of the operation during the actual EES is built.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.24 no.65
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• pp.65-73
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• 2001

In this study, psychophysiological stress was quantitatively evaluated at various car interior noise levels by using Electroencephalogram(EEG). An experiment was performed to investigate the most comfortable range of noise level during simulated driving condition. Twelve healthy volunteers participated in the experiment. They were asked to operate the driving simulator while six levels of interior noise were given, such as 45dB(A), 50dB(A), 55dB(A), 60dB(A), 70dB(A), 80dB(A), and maximal subjective noise level. EEG signals were recorded for 60 seconds in each noise level. The power spectral analysis was performed to analyze EEG signal. At the same time, psychological stress was also measured subjectively by using a magnitude estimation method. The results showed that subjective stress and EEG spectrum indicated a statistically significant difference between noise levels. In particular, high level noise produced an increase in beta power at temporal(T3, T4) areas. It was also found that beta activity was highly correlated with subjective perception of discomfort, and subjects responded to car interior noise as arousing or negative stimuli. Moreover, beta power remained stable above 70dB(A), whereas subjective discomfort continued to increase even above 70dB(A) We concluded that brain waves could provide psychophysiological information of drivers emotional reaction to car interior noise. Thus, EEG parameters could be a new measure to determine optimal noise level in ergonomic workplace design after further verification in various experimental conditions.

• KSCI Review
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• v.2 no.1
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• pp.121-129
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• 1995

Fault simulation of logic circuits is an important part of the test-generation process. It is used for the propose of generation fault dictionaries or for the verification of the adequacy of tests. In this paper, a backtrace fault simulation is proposed to test generation. This is consists of 3 part ; initialization phase for given circuit, backtrace fault simulation phase to find fault list and reevaluation phase to list event. The main idea of this algorithm is to retain a minimum fault list by cutting uncontrollable lines of path when a logic event occurs in backward tracing phases. And the simulator is revaluates a fault list associated with the output of an element only if logic event occurs at any of its inputs when a list event occurs at one of its primary inputs. It reguires a O(n) memory space complexity. where n is a number of signal lines for the given circuits. Several examples are given to illustrate the power of this algorithm.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.6
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• pp.3000-3022
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• 2019

Full-duplex (FD) technologies enable wireless nodes to simultaneously transmit and receive signal using the same frequency-band. The FD modes could improve their physical layer throughputs. However, in the wireless ad hoc networks, the FD communications also produce new interference risks. On the one hand, the interference ranges (IRs) of the nodes are enlarged when they work in the FD mode. On the other hand, for each FD pair, the FD communication may cause the potential hidden terminal problems to appear around the both sides. In this paper, to avoid the interference risks, we first model the IR of each node when it works in the FD mode, and then analyze the conditions to be satisfied among the transmission ranges (TRs), carrier-sensing ranges (CSRs), and IRs of the FD pair. Furthermore, in the media access control (MAC) layer, we propose a specific method and protocol for collision avoidance. Based on the modified Omnet++ simulator, we conduct the simulations to validate and evaluate the proposed FD MAC protocol, showing that it can reduce the collisions effectively. When the hidden terminal problem is serious, compared with the existing typical FD MAC protocol, our protocol can increase the system throughput by 80%~90%.

• Journal of Information Processing Systems
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• v.15 no.3
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• pp.670-681
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• 2019

Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

• International Journal of Advanced Culture Technology
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• v.6 no.4
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• pp.52-57
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• 2018

The purpose of this paper is to develop simulations that can be used for virtual education in dentistry. The virtual education to be developed will be developed with clinical training and actual case data of tooth extraction. This development goal is to allow dental students to learn the necessary surgical techniques at the point of their choice, not going into the operating room, away from time, space, and physical limits. I want to develop content using VR. Oculus Rift HMD, Optical Based Outside-in Tracking System, Oculus Touch Motion Controller, and Headset as Input / Output Device. In this configuration, the optimization method is applied convergent, and when the operation of the VR contents is performed, the content data is extracted from the interaction analysis formed in the VR engine, and the data is processed by the content algorithm. It also computes events and dental operations generated within the 3D engine programming and generates corresponding events through data processing according to the input signal. The visualization information is output to the HMD using the rendering information. In addition, the operating room environment was constructed by studying lighting and material for actual operating room environment. We applied the ratio of actual space to virtual space and the ratio between character and actual person to create a spatial composition at a similar rate to actual space.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.2
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• pp.136-146
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• 2013

In this paper, the residual delay compensation algorithm is proposed for FX-type KJJVC. In case of initial version as that design algorithm of KJJVC, the integer calculation and the cos/sin table for the phase compensation coefficient were introduced in order to speed up of calculation. The mismatch between data timing and residual delay phase and also between bit-jump and residual delay phase were found and fixed. In final design of KJJVC residual delay compensation algorithm, the initialization problem on the rotation memory of residual delay compensation was found when the residual delay compensated value was applied to FFT-segment, and this problem is also fixed by modifying the FPGA code. Using the proposed residual delay compensation algorithm, the band shape of cross power spectrum becomes flat, which means there is no significant loss over the whole bandwidth. To verify the effectiveness of proposed residual delay compensation algorithm, we conducted the correlation experiments for real observation data using the simulator and KJJVC. We confirmed that the designed residual delay compensation algorithm is well applied in KJJVC, and the signal to noise ratio increases by about 8%.

• Journal of Korean Society of Transportation
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• v.25 no.6
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• pp.185-196
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• 2007

The aim of this research is to develop a signal control algorithm using internal metering to minimize total delay that vehicles go through, in case a network is oversaturated. To calculate total delay on the network, the authors first detect vehicles' arrivals and departures in the network through the detecting system, and chase the vehicles' flow in the links with a platoon dispersion model. Following these, the authors calculate the queue length in all the inks of the network through the chase of vehicles, deduce the stopped time delay, and finally convert the stopped time delay to the approach delay with a time-space diagram. Based on this calculated delay, an algorithm that calculates the level of the internal metering necessary to minimize the deduced approach delay is suggested. To verify effectiveness of this suggested algorithm, the authors also conduct simulation with the micro-simulator VISSIM. The result of the simulation shows that the average delay per vehicle is 82.3 sec/veh and this delay is lower than COSMOS (89.9sec/veh) and TOD (99.1sec/veh). It is concluded that this new signal control algorithm suggested in this paper is more effective in controlling an oversaturated network.