• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.12
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• pp.611-623
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• 2002

This paper introduce the real time digital simulator which is located in Korea Electric Power Research Institute. This paper also describes the methodology for the performance test of the PSS using KEPS. This test is to get a high degree of the confidence of the developed PSS before it is installed into the real power system. This has been performed in the form of closed-loop tests in which Simulator and PSS are connected and signals come and back interactively. Many tests have successfully done using KEPS which consists of 26 RTDS racks, under the large-scale power system. The simulated reduced KEPCO power system contains 88 generators and 295 buses. Through the AVR step, three phase fault and active power variation test, the effectiveness of developed PSS has been proved. This paper also presents the overview of KEPS and hardware of protype PSS.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.29 no.3
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• pp.111-118
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• 2006

This paper presents design and development of a simulator evaluates the performance of a hierarchical cellular system. The proposed hierarchical cellular simulator, consisting of macro, micro, and pico cells, applies the wrap-around technique to reduce simulation time. The simulator is implemented as object oriented class models by using the C++ language in a PC environment. The resulting application can evaluate the interference, SIR(Signal to Interference Ratio), and capacity of a hierarchical cellular system in various configurations. Moreover, it can be used in other applications such as power control, call admission control, hand over scheme.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.7
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• pp.1026-1030
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• 2015

In this paper, we propose a signal processing board of an optical delay simulator for evaluating a long-range laser range finder and a laser target designator. We improved the accuracy by applying the clock multiplication and the correction of error gradient. To evaluate the performance of the proposed method, we implemented a prototype board and performed experiments. As a result, we implemented the optical delay simulator with resolution less than 0.7m in measuring distance 60km and a standard deviation of 0.041m. The PRF code detection logic and generation logic have a stability less than 0.03% and 0.08% compared to the NATO standard, respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.3
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• pp.95-99
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• 2013

The maximum power analysis simulator took advantage of the facilities and power consumption reduction simulator test scenario development and testing of improvement in the scenario. As a maximum demand power controller, Maximum power analysis simulator performs control and disperasion of maximum demand power by calculating base power, load forecast, and present power which are based on signal of watt-hour meter to keep the electricity under the target. In addition, various algorithms to select appropriate control methode on each of the light installations through the peak demand power is configured to management. The simulation shows the success of control power for the specified target controlled by five sequential lighting installations.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.8
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• pp.94-99
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• 2000

In this study applied the general controller into th 16bit ordinary controller and recommand the simulator features the real system's propeties without DSP(Digital Signal Processing)-card. This simulator is designed to be synchronized in real time using A/D(Analog-Digital) convert and D/A(Digital-Analong) convert. In this study DSP card which is usually used for complex calculation is replaced with personal computer and designed to control, control-force using with the 16-bit micro processor.

• Journal of the Korean Society for Nondestructive Testing
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• v.22 no.6
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• pp.649-658
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• 2002

As an attempt to further improve the reliability and effectiveness of ultrasonic testing (UT), a two-dimensional numerical simulator of UT was developed. The simulator models the wave medium (or test object) using the mass-spring lattice model (MSLM) that consists of mass-points and springs. Some previous simulation results, obtained by using MSLM, are briefly reviewed in this paper, for propagation, reflection, and scattering of ultrasonic waves. Next, the models of transmitting and receiving piezoelectric transducers are introduced with some numerical results, which is a main focus of this paper. The UT simulator, established by combining the transducer models with the MSLM, was used to simulate many UT setups. In this paper, two simple setups are considered as examples, and their simulated A-scan signals are discussed. The potential of the MSLM, transducer models, and the UT simulator developed in this study to be used in the actual UT is confirmed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.347-354
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• 1987

Timing simulators are widely used nowadays for analyzing large-scale MOS digital circuits, which, however, have several limitations such as nonconvergence and/or in accuracy for circuits containing tightly coupled feedback elements or loops. This paper describes a new timing simulator which aims at solving these problems. The algorithm employed is based on the wave-form relaxation method, but exploits the signal flow along the feedback loops. Each of feedback loops is treated as one circuit block and then local iterations are performed to enhance the timing simulation. With these techniques, out simulator can analyze the MOS digital circuits with up to 5-20 times of the magnitude speed improvemnets as compared to SPICE2, while maintaining the accuracy.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.5
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• pp.842-849
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• 2011

The transponder simulator designed to simulate the transponder of military satellite communication systems in the geostationary orbit is required to have time delay function, because of 250 ms delay time, when a radio wave transmits the distance of 36,000 km in free space. But, it is very difficult to develop 250 ms time delay device in the transponder simulator of 100 MHz bandwidth, due to unstable operation of FPGA, loss of memory data for the high speed rate signal processing. Up to date, bandwidth of the time delay device is limited to 45 MHz bandwidth. To solve this problem, we propose the new time delay techniques up to 100 MHz bandwidth without data loss. Proposed techniques are the low speed down scaling and high speed up scaling methods to read and write the external memory, and the matrix structure design of FPGA memory to treat data as high speed rate. We developed the satellite link simulator in 100 MHz bandwidth using the proposed new time delay techniques, implemented to the transponder simulator and verified the function of 265 ms time delay device in 100 MHz bandwidth.

• Transactions of the Korean Society of Automotive Engineers
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• v.17 no.4
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• pp.16-23
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• 2009

Driving simulators are useful tools not only to test the components of future cars but also to evaluate the telematics service and HMI (Human-Machine Interface). However driving simulators cannot be implemented to test and evaluate the telematics service system because the GPS (Global Positioning System) which contains basic functional support for the telematics module do not work in the VR (virtual reality) environment. This paper presents a method to implement telematics service to a driving simulator by developing the GPS simulator which is able to emulate GPS satellite signals consist of NMEA-0183 protocol and RS232C communication standards. It is expected that the driving simulator with the GPS simulator can be used to study HMI and human-factor evaluations of the commercial telematics system to realize the HiLES (Human-in-the-Loop Evaluation System).

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.1
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• pp.84-91
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• 2005

In this paper, we describe the real-time parallel processing simulator developed for the use of performance analysis of rolling missiles. The real-time parallel processing simulator developed here consists of seeker emulator generating infrared image signal on aircraft, real-time computer, host computer, system unit, and actual equipments such as auto-pilot processor and seeker processor. Software is developed from mathematic models, 6 degree-of-freedom module, aerodynamic module which are resided in real-time computer, and graphic user interface program resided in host computer. The real-time computer consists of six TIC-40 processors connected in parallel. The seeker emulator is designed by using analog circuits coupled with mechanical equipments. The system unit provides interface function to match impedance between the components and processes very small electrical signals. Also real launch unit of missiles is interfaced to simulator through system unit. In order to apply the real-time parallel processing simulator to performance analysis equipment of rolling missiles it is essential to perform the performance verification test of simulator.