• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1418-1419
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• 2011

차세대 전력 반도체인 고전압 GaN 쇼트키 장벽 다이오드의 역방향 특성을 개선하기 위해서 열 산화공정이 제안되었다. AlGaN/GaN 에피탁시 위에 쇼트키 장벽 다이오드 구조가 제작되었으며, 쇼트키 컨택은 증착 후 $450^{\circ}C$에서 산화되었다. 열 산화공정이 메사 측벽의 AlGaN 및 GaN 표면에 $AlO_x$ 및 $GaO_x$를 형성하여 표면으로 흐르는 누설전류를 억제한다. 표면 및 GaN 버퍼를 통한 누설전류는 열 산화 공정 이후 100 ${\mu}m$-너비당 51.3 nA에서 24.9 pA로 1/2000 배 수준으로 감소하였다. 표면 산화물 형성으로 인하여 생성된 Ga-vacancy와 Al-vacancy는 acceptor로 동작하여 surface band bending을 증가시켜 쇼트키 장벽 높이를 증가시킨다. 애노드-캐소드 간격이 5 ${\mu}m$인 제작된 소자는 0.99 eV의 높은 쇼트키 장벽 높이를 획득하여, -100 V에서 0.002 A/$cm^2$의 낮은 누설전류를 확보하였다. 애노드-캐소드 간격이 5에서 10, 20, 50 ${\mu}m$로 증가되면 소자의 항복전압은 348 V에서 396, 606, 941 V로 증가되었다. 열 산화공정은 전력용 GaN 전자소자의 누설전류감소와 항복전압 증가를 위한 후처리 공정으로 적합하다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.68-68
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• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.1
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• pp.39-46
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• 2021

The quantitative measurement of interfacial adhesion energy (Gc) of multilayer thin films for Cu interconnects was investigated using a double cantilever beam (DCB) and 4-point bending (4-PB) test. In the case of a sample with Ta diffusion barrier applied, all Gc values measured by the DCB and 4-PB tests were higher than 5 J/㎡, which is the minimum criterion for Cu/low-k integration without delamination. However, in the case of the Ta/Cu sample, measured Gc value of the DCB test was lower than 5 J/㎡. All Gc values measured by the 4-PB test were higher than those of the DCB test. Measured Gc values increase with increasing phase angle, that is, 4-PB test higher than DCB test due to increasing plastic energy dissipation and roughness-related shielding effects, which matches well interfacial fracture mechanics theory. As a result of the 4-PB test, Ta/Cu and Cu/Ta interfaces measured Gc values were higher than 5 J/㎡, suggesting that Ta is considered to be applicable as a diffusion barrier and a capping layer for Cu interconnects. The 4-PB test method is recommended for quantitative adhesion energy measurement of the Cu interconnect interface because the thermal stress due to the difference in coefficient of thermal expansion and the delamination due to chemical mechanical polishing have a large effect of the mixing mode including shear stress.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.139-141
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• 2005

It is possble to study charge transfer property which is caused by height variation because we can see the organic materials barrier height and STM tip by organic materials energy band gap. Here, we investigated the negative differential resistance(NDR) and charge transfer property of self-assembled 4,4-Di(ethynylphenyl)-2'-nitro-1-(thioacetyl)benzene, which has been well known as a conducting molecule. Self-assembly monolayers(SAMs) were prepared on Au(111), which had been thermally deposited onto pre-treatment($H_{2}SO_{4}:H_{2}O_{2}$=3:1) Si. The Au substrate was exposed to a 1 mM/l solution of 1-dodecanethiol in ethanol for 24 hours to form a monolayer. After thorough rinsing the sample, it was exposed to a $0.1{\mu}M/1$ solution of 4,4-Di(ethynylphenyl)-2'-nitro-1-(thioacetyl)benzene in dimethylformamide(DMF) for 30 min and kept in the dark during immersion to avoid photo-oxidation. After the assembly, the samples were removed from the solutions, rinsed thoroughly with methanol, acetone, and $CH_{2}Cl_{2}$, and finally blown dry with $N_2$. Under these conditions, we measured electrical properties of self-assembly monolayers(SAMs) using ultra high vacuum scanning tunneling microscopy(UHV-STM). The applied voltages were from -1.50 V to -1.20 V with 298 K temperature. The vacuum condition is $6{\times}10^{-8}$ Torr. As a result, we found that NDR and charge transfer property by a little change of height when the voltage is applied between STM tip and electrode.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.38.2-38.2
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• 2011

폴리머 박막은 그 고유한 특성으로 인해 여러 산업적으로 널리 사용되고 있는 재료이다 예로 의약품이나 식품 포장지의 배리어, 전자부품의 절연체, 반도체 공정에서의 사용, 혹은 부식방지를 위해 사용 되어지기도 한다. 이 폴리머 박막을 증착 하기 위한 방법으로 이전부터 CVD (Chemical Vapor Deposition) 방법이 많이 사용되었고 지금까지도 가장 많이 사용되는 방법이다. CVD를 사용하여 $SiO_2$-like 필름의 증착은 전구체(precursor)로 Silane ($SiH_4$)을 사용하였으며, 플라즈마 발생 소스(source)로 열 혹은 전기장 등을 사용 하며 공정 시 압력 또한 대부분 저압 하에서 실시 하였다. 이와 같은 이전 CVD 방법의 문제는 사용되는 Silane 자체가 인체에 해로울 정도로 독성이 있으며 폭발성도 같이 가지고 있어 작업환경의 위험성이 높으며 열을 사용한 CVD의 경우 높은 공정 온도로 인해 증착 할 수 있는 대상이 제한 되어 지며 높은 열의 발생을 위해 많은 에너지의 소비가 필요하다. 저압 플라즈마를 사용한 CVD 는 공정상 높은 열의 발생이 일어나지 않아 기판 운용상 문제가 되지 않지만 저압 환경에서 해당 공정이 이루어기 때문에 인해 필수적으로 고가의 진공 챔버가 필수적이며 저압을 유지할 고가의 진공 펌프나 추가 장비들이 필요하게 된다, 또한 챔버 내에서 이루어지는 공정으로 인해 공정의 연속성이 떨어져 시잔비용 또한 많이 잡아 먹는다. 이러한 열 혹은 저압 플라즈마등을 사용한 공정의 단점을 해결하기 위해 여러 연구자들이 다양한 방법을 통해 연구를 하였다. 대기압 유전체 배리어 방전(AP-DBD: Atmospheric Pressure-Dielectric Barrier Discharge)을 사용한 폴리머 박막의 증착은 이전 전통적인 방법에 비해 낮은 장비 가격과 낮은 공정 온도 그리고 연속적인 공정 등의 장점이 있는 폴리머 박막 증착 방법 이다. 대기압 유전체 배리어 방전 공정 변수로 공급 전압 및 주파수 그리고 공급 전압의 영향, 전구체를 유전체 배리어 방전 전극으로 이동 시키기 위해 사용된 캐리어 가스의 종류 및 유량, 화학양론적 계수를 맞추기 위해 같이 포함되는 산소 가스의 유량, DBD 전극의 형태에 따른 증착 박막의 균일성 등 이 존재하며 이런 많은 변수 들에 대한 연구가 진행 되었지만 아직 이 대기압 DBD를 이용한 폴리머 박막의 증착에 대한 명확한 이해는 아직 완전 하다 할 수 없다. 본 연구에서는 이러한 대기압 DBD를 이용하여 폴리머 박막의 증착시 영향을 미치는 많은 공정 변수 등이 박막생성에 미치는 영향과 증착된 박막의 성질에 대한 연구를 진행 하였다.

• Journal of the Korean Magnetics Society
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• v.14 no.3
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• pp.99-104
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• 2004

We have studied to understand the barrier and interface qualities and structural changes through measuring temperature dependent spin-polarization as functions of plasma oxidation time and annealing time. Magnetic tunnel junctions consisting of SiO2$_2$/Ta 5/CoFe 17/IrMn 7.5/CoFe 5/Al 1.6-Ox/CoFe 5/Ta 5 (numbers in nm) were deposited and annealed when necessary. A 30 s,40 s oxidized sample showed the lowest spin-polarization values. It is presumed that tunneling electrons were depolarized and scattered by residual paramagnetic Al due to under-oxidation. On the contrary, a 60s, 70 s oxidized sample might have experienced over-oxidation, where partially oxidized magnetic dead layer was formed on top of the bottom CoFe electrode. The magnetic dead layer is known to increase the probability of spin-flip scattering. Therefore it showed a higher temperature dependence than that of the optimum sample (50 s oxidation). temperature dependence of 450 K annealed samples was improved when the as-deposited one compared. But the sample underwent 475 K and 500 K annealing exhibits inferior temperature dependence of spin-polarization, indicating that the over-annealed sample became microstucturally degraded.