• 한국정보전자통신기술학회논문지
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• 제12권5호
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• pp.499-506
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• 2019

본 논문은 SiC Hybrid module를 적용한 7kW 인버터의 동작 안정성에 관한 것으로 손실 방정식과 시뮬레이션 결과를 비교하여 시뮬레이션 결과의 유효성을 검증하였으며, 시뮬레이션을 통해 Si module과 SiC Hybrid module의 스위치 손실과 다이오드 손실을 비교하였다. 손실 방정식 계산을 통하여 SiC Hybrid module의 도통 손실은 168W, 스위칭 손실은 9.3W, 다이오드 손실은 10.5nW의 결과를 나타내었으며, 시뮬레이션 결과와 비교하였을 때 유사한 값을 나타내었다. 이를 바탕으로 Si module과 SiC Hybrid module의 시뮬레이션 결과 값 비교 결과, Si module의 총 소자 손실값은 246.2W, SiC Hybrid module의 총 소자 손실 값은 189.9W를 나타내었으며, 손실 차이 값은 56.3W로써 약 0.8W의 효율 차이를 보였다. 이로 인하여 SiC SBD의 Reverse recovery 특성을 검증하였다. 또한 고온 포화상태에서 SiC Hybrid module 및 Si module의 안정성을 확인하기 위하여 온도 포화 테스트를 진행하였으며, Si module의 경우, 출력전력 4kW에서 동작을 멈추었고, SiC Hybrid module은 7kW까지 동작을 확인하였다. 이를 바탕으로, 효율 그래프와 온도 그래프를 제시하였으며, Si module은 4kW까지, SiC Hybrid module은 7kW까지 그래프로 나타내었다.

• Journal of the Korean Physical Society
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• 제73권9호
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• pp.1356-1361
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• 2018

Replacing conventional Si diodes with SiC diodes in Si insulated gate bipolar transistor (IGBT) modules is advantageous as it can reduce power losses significantly. Also, the fast switching nature of the SiC diode will allow Si IGBTs to operate at their full high-switching-speed potential, which at present conventional Si diodes cannot do. In this work, the electrical test results for Si-IGBT/4HSiC-Schottky hybrid substrates (hybrid SiC substrates) are presented. These substrates are built for two voltage ratings, 1.7 kV and 3.3 kV. Comparisons of the 1.7 kV and the 3.3 kV Si-IGBT/Si-diode substrates (Si substrates) at room temperature ($20^{\circ}C$, RT) and high temperature ($H125^{\circ}C$, HT) have shown that the switching losses in hybrid SiC substrates are miniscule as compared to those in Si substrates but necessary steps are required to mitigate the ringing observed in the current waveforms. Also, the effect of design variations on the electrical performance of 1.7 kV, 50 A diodes is reported here. These variations are made in the active and termination regions of the device.

• Advances in nano research
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• 제2권1호
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• pp.23-56
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• 2014

The significant growth of the Si photovoltaic industry has been so far limited due to the high cost of the Si photovoltaic system. In this regard, the most expensive factors are the intrinsic cost of silicon material and the Si solar cell fabrication processes. Conventional Si solar cells have p-n junctions inside for an efficient extraction of light-generated charge carriers. However, the p-n junction is normally formed through very expensive processes requiring very high temperature (${\sim}1000^{\circ}C$). Therefore, several systems are currently under study to form heterojunctions at low temperatures. Among them, carbon nanotube (CNT)/Si hybrid solar cells are very promising, with power conversion efficiency up to 15%. In these cells, the p-type Si layer is replaced by a semitransparent CNT film deposited at room temperature on the n-doped Si wafer, thus giving rise to an overall reduction of the total Si thickness and to the fabrication of a device with cheaper methods at low temperatures. In particular, the CNT film coating the Si wafer acts as a conductive electrode for charge carrier collection and establishes a built-in voltage for separating photocarriers. Moreover, due to the CNT film optical semitransparency, most of the incoming light is absorbed in Si; thus the efficiency of the CNT/Si device is in principle comparable to that of a conventional Si one. In this paper an overview of several factors at the basis of this device operation and of the suggested improvements to its architecture is given. In addition, still open physical/technological issues are also addressed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.240.2-240.2
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• 2013

The device scale of flash memory was confronted with quantum mechanical limitation. The next generation memory device will be required a break-through for the device scaling problem. Especially, graphene is one of important materials to overcome scaling and operation problem for the memory device, because ofthe high carrier mobility, the mechanicalflexibility, the one atomic layer thick and versatile chemistry. We demonstrate the hybrid memory consisted with the metal-oxide quantum dots and the mono-layered graphene which was transferred to $SiO_2$ (5 nm)/Si substrate. The 5-nm thick secondary $SiO_2$ layer was deposited on the mono-layered graphene by using ultra-high vacuum sputtering system which base pressure is about $1{\times}10^{-10}$ Torr. The $In_2O_3$ quantum dots were distributed on the secondary $SiO_2$2 layer after chemical reaction between deposited In layer and polyamic acid layer through soft baking at $125^{\circ}C$ for 30 min and curing process at $400^{\circ}C$ for 1 hr by using the furnace in $N_2$ ambient. The memory devices with the $In_2O_3$ quantum dots on graphene monolayer between $SiO_2$ thin films have demonstrated and evaluated for the application of next generation nonvolatile memory device. We will discuss the electrical properties to understating memory effect related with quantum mechanical transport between the $In_2O_3$ quantum dots and the Fermi level of graphene layer.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.768-771
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• 2006

Uniformity and performance characteristics of LTPS TFTs are important parameters for making advanced active-matrix displays. In this paper, we describe an SLS-based crystallization approach for producing orientation-controlled Si films with reduced concentrations of planar defects that stand to potentially deliver unprecedented levels of device uniformity and performance. Specifically, a 2-step process referred to as hybrid SLS has been developed that produces a variety of high-quality {100} surface-oriented Si films.

• Progress in Superconductivity
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• 제9권2호
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• pp.177-182
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• 2008

[ $MgB_2$ ] thin films were fabricated using hybrid physical-chemical vapor deposition (HPCVD) method on silicon substrates with buffers of alumina grown by using atomic layer deposition method. The growth war in a range of temperatures $500\;{\sim}\;600^{\circ}C$ and under the reactor pressures of $25\;{\sim}\;50\;Torr$. There are some interfacial reactions in the as-grown films with impurities of mostly $Mg_2Si$, $MgAl_2O_4$, and other phases. The $T_c$'s of $MgB_2$ films were observed to be as high as 39 K, but the transition widths were increased with growth temperatures. The magnetization was measured as a function of temperature down to the temperature of 5 K, but the complete Meissner effect was not observed, which shows that the granular nature of weak links is prevailing. The formation of mostly $Mg_2Si$ impurity in HPCVD process is discussed, considering the diffusion and reaction of Mg vapor with silicon substrates.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.396-396
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• 2013

The resistive random access memory (ReRAM) has several advantages to apply next generation non-volatile memory device, because of fast switching time, long retentions, and large memory windows. The high mobility of monolayered graphene showed several possibilities for scale down and electrical property enhancement of memory device. In this study, the monolayered graphene grown by chemical vapor deposition was transferred to $SiO_2$ (100 nm)/Si substrate and glass by using PMMA coating method. For formation of metal-oxide nanoparticles, we used a chemical reaction between metal films and polyamic acid layer. The 50-nm thick BPDA-PDA polyamic acid layer was coated on the graphene layer. Through soft baking at $125^{\circ}C$ or 30 min, solvent in polyimide layer was removed. Then, 5-nm-thick indium layer was deposited by using thermal evaporator at room temperature. And then, the second polyimide layer was coated on the indium thin film. After remove solvent and open bottom graphene layer, the samples were annealed at $400^{\circ}C$ or 1 hr by using furnace in $N_2$ ambient. The average diameter and density of nanoparticle were depending on annealing temperature and times. During annealing process, the metal and oxygen ions combined to create $In_2O_3$ nanoparticle in the polyimide layer. The electrical properties of $In_2O_3$ nanoparticle ReRAM such as current-voltage curve, operation speed and retention discussed for applictions of transparent and flexible hybrid ReRAM device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.158-158
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• 2012

A new kind of organic-inorganic hybrid polymer, poly(tetraphenyl)silole siloxane (PSS), was invented and synthesized for realization of its unique charge trap properties. The organic portions consisting of (tetraphenyl)silole rings are responsible for electron trapping owing to their low-lying LUMO, while the Si-O-Si inorganic linkages of high HOMO-LUMO gap provide the intrachain energy barrier for controlling electron transport. Such an alternation of the organic and inorganic moieties in a polymer may give an interesting quantum well electronic structure in a molecule. The PSS thin film was fabricated by spin-coating of the PSS solution in THF organic solvent onto Si-wafer substrates and curing. The electron trapping of the PSS thin films was confirmed by the capacitance-voltage (C-V) measurements performed within the metal-insulator-semiconductor (MIS) device structure. And the quantum well electronic structure of the PSS thin film, which was thought to be the origin of the electron trapping, was investigated by a combination of theoretical and experimental methods: density functional theory (DFT) calculations in Gaussian03 package and spectroscopic techniques such as near edge X-ray absorption fine structure spectroscopy (NEXAFS) and photoemission spectroscopy (PES). The electron trapping properties of the PSS thin film of quantum well structure are closely related to intra- and inter-polymer chain electron transports. Among them, the intra-chain electron transport was theoretically studied using the Atomistix Toolkit (ATK) software based on the non-equilibrium Green's function (NEGF) method in conjunction with the DFT.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• 마이크로전자및패키징학회지
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• 제21권4호
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• pp.1-13
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• 2014

The paper gives an overview of the concepts, basic requirements, and trends regarding packaging technologies of power modules in hybrid (HEV) and electric vehicles (EV). Power electronics is gaining more and more importance in the automotive sector due to the slow but steady progress of introducing partially or even fully electric powered vehicles. The demands for power electronic devices and systems are manifold, and concerns besides aspects such as energy efficiency, cooling and costs especially robustness and lifetime issues. Higher operation temperatures and the current density increase of new IGBT (Insulated Gate Bipolar Transistor) generations make it more and more complicated to meet the quality requirements for power electronic modules. Especially the increasing heat dissipation inside the silicon (Si) leads to maximum operation temperatures of nearly $200^{\circ}C$. As a result new packaging technologies are needed to face the demands of power modules in the future. Wide-band gap (WBG) semiconductors such as silicon carbide (SiC) or gallium nitride (GaN) have the potential to considerably enhance the energy efficiency and to reduce the weight of power electronic systems in EVs due to their improved electrical and thermal properties in comparison to Si based solutions. In this paper, we will introduce various package materials, advanced packaging technologies, heat dissipation and thermal management of advanced power modules with extended reliability for EV applications. In addition, SiC and GaN based WBG power modules will be introduced.