• 반도체디스플레이기술학회지
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• 제15권3호
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• pp.72-77
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• 2016

As the semiconductor production technology has gradually developed and intra-market competition has grown fiercer, the caliber of Si Wafer for semiconductor production has increased as well. And semiconductors have become integrated with higher density. Presently the Si Wafer caliber has reached up to 450 mm and relevant production technology has been advanced together. Electrostatic chuck is an important device utilized not only for the Wafer transport and fixation but also for the heat treatment process based on plasma. To effectively control the high calories generated by plasma, it employs a refrigerant-based cooling method. Amid the enlarging Si Wafers and semiconductor device integration, effective temperature control is essential. Therefore, uniformed temperature distribution in the electrostatic chuck is a key factor determining its performance. In this study, the form of refrigerant flow channel will be investigated for uniformed temperature distribution in electrostatic chuck.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2000년도 춘계학술발표회 초록집
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• pp.43-44
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• 2000

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2003년도 춘계학술발표회 초록집
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• pp.45-47
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• 2003

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회B
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• pp.2032-2037
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• 2007

Numerical analysis was conducted to investigate the atomic layer deposition(ALD) of silicon nitride using silane and ammonia as precursors. The present study simulated the surface reactions for as-deposited $Si_3N_4$ as well as the kinetics for the reactions of $SiH_4$ and $NH_3$on the semiconductor wafer. The present numerical results showed that the ALD process is dependent on the activation constant. It was also shown that the low activation constant leads to the self-limiting reaction required for the ALD process. The inlet and wafer temperatures were 473 K and 823 K, respectively. The system pressure is 2 Torr.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.16-17
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• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 추계학술대회 초록집
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• pp.46.1-46.1
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• 2010

Surface passivation of crystalline silicon(c-Si) surface with a-Si:H thin films has been investigated by using quasi-steady-state photo conductance(QSSPC) measurements. Analyzing the influence of a-Si:H film thickness, process gas ratio, deposition temperature and post annealing temperature on the passivation properties of c-Si, we optimized the passivation conditions at the substrate temperature of $200-250^{\circ}C$. Best surface passivation has been obtained by post-deposition annealing of a-Si:H film layer. Post annealing around the deposition temperature was sufficient to improve the surface passivation for silicon substrates. We obtained effective carrier lifetimes above 5.5 ms on average.

• 마이크로전자및패키징학회지
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• 제20권2호
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• pp.47-51
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• 2013

본 연구에서는 웨이퍼 레벨 Cu 본딩을 이용한 3D 적층 IC의 개발을 위해 2단계 기계적 화학적 연마법(CMP)을 제안하고 그 결과를 고찰하였다. 다마신(damascene) 공정을 이용한 $Cu/SiO_2$ 복합 계면에서의 Cu dishing을 최소화하기 위해 Cu CMP 후 $SiO_2$ CMP를 추가로 시행하였으며, 이를 통해 Cu dishing을 $100{\sim}200{\AA}$까지 낮출 수 있었다. Cu 범프의 표면거칠기도 동시에 개선되었음을 AFM 관찰을 통해 확인하였다. 2단 CMP를 적용하여 진행한 웨이퍼 레벨 Cu 본딩에서는 dishing이나 접합 계면이 관찰되지 않아 2단 CMP 공정이 성공적으로 적용되었음을 확인할 수 있었다.

• 한국전기전자재료학회논문지
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• 제15권4호
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• pp.301-307
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• 2002

Direct bonded SOI wafer pairs with $Si ll SiO_2/Si_3N_4 ll Si$ the heterogeneous insulating layers of SiO$_2$-Si$_3$N$_4$are able to apply to the micropumps and MEMS applications. Direct bonding should be executed at low temperature to avoid the warpage of the wafer pairs and inter-diffusion of materials at the interface. 10 cm diameter 2000 ${\AA}-SiO_2/Si(100}$ and 560 $\AA$- ${\AA}-Si_3N_4/Si(100}$ wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were pre- mated with facing the mirror planes by a specially designed aligner in class-100 clean room immediately. We employed a heat treatment equipment so called fast linear annealing(FLA) with a halogen lamp to enhance the bonding of pre mated wafers We kept the scan velocity of 0.08 mm/sec, which implied bonding process time of 125 sec/wafer pairs, by varying the heat input at the range of 320~550 W. We measured the bonding area by using the infrared camera and the bonding strength by the razor blade clack opening method, respective1y. It was confirmed that the bonding area was between 80% and to 95% as FLA heat input increased. The bonding strength became the equal of $1000^{\circ}C$ heat treated $Si ll SiO_2/Si_3N_4 ll Si$ pair by an electric furnace. Bonding strength increased to 2500 mJ/$\textrm{m}^2$as heat input increased, which is identical value of annealing at $1000^{\circ}C$-2 hr with an electric furnace. Our results implies that we obtained the enough bonding strength using the FLA, in less process time of 125 seconds and at lowed annealing temperature of $400^{\circ}C$, comparing with the conventional electric furnace annealing.

• Bulletin of the Korean Chemical Society
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• 제35권1호
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• pp.35-38
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• 2014

Herein, we report on the preparation of red fluorescent Si nanoparticles stabilized with styrene. Nano-sized Si particles emit fluorescence under UV excitation, which could be used to open up new applications in the fields of optics and semi-conductor research. Unfortunately, conventional methods for the preparation of red fluorescent Si nanoparticles suffer from the lack of a fully-established standard synthesis protocol. A common initial approach during the preparation of semi-conductors is the etching of crystalline Si wafers in a HF/ethanol/$H_2O$ bath, which provides a uniformly-etched surface of nanopores amenable for further nano-sized modifications via tuning of various parameters. Subsequent sonication of the etched surface crumbles the pores on the wafer, resulting in the dispersion of particles into the solution. In this study, we use styrene to occupy these platforms to stabilize the surface. We determine that the liberated silicon particles in ethanol solution interact with styrene, resulting in the substitution of Si-H bonds with those of Si-C as determined via UV photo-catalysis. The synthesized styrene-coated Si nanoparticles exhibit a stable, bright, red fluorescence under excitation with a 365 nm UV light, and yield approximately 100 mg per wafer with a synthesis time of 2 h. We believe this protocol could be further expanded as a cost-effective and high-throughput standard method in the preparation of red fluorescent Si nanoparticles.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2010년도 추계학술대회 초록집
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• pp.38.1-38.1
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• 2010

The trend to thinner crystalline silicon solar wafers in production of solar cells investigates re-evolution of back surface field (BSF) formation. We have studied mechanisms of back contact formation in Al evaporation and screen printed Al paste for Si solar cells by TEM analysis. We observed that Si diffuse into Al during heat up. The Si diffusion process made vacancies in Si wafer. The Al began to seep into the Si wafer (Al spike). During heat down, the Al spike were shrink which causes the doped region (BSF).