• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.59 no.1
• /
• pp.130-133
• /
• 2010

Although many structures based on $SnO_2$ nanowires have been demonstrated, there is a limitation towards practical application due to the unwanted contact potential between the metal electrode and the $SnO_2$ nanowire. This is mostly due to the presence of the native oxide layer that acts as an insulator between the metal contact and the nanowire. In this study the contact properties between Ti/Au contacts and a single $SnO_2$ nanowire was compared to the electrical properties of a contact without the oxide layer. RIE(Reactive Ion Etching) is used to selectively remove the oxide layer from the contact area. The $SnO_2$ nanowires were synthesized by chemical vapor deposition (CVD) and dispersed on a $Si/Si_3N_4$ substrate. The Ti/Au (20nm/100nm) electrodes were formed bye-beam lithography, e-beam evaporation and a lift-off process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.178-179
• /
• 2006

나노 크기를 가지는 DNA 분자를 template로 사용하여 전도성 고분자의 일종인 polypyrrole nanowire를 합성하였다. 본 논문에서 합성된 polypyrrole nanowire는 단량체인 pyrrole과 산화제와의 화학적인 반응에 의해 만들어졌다. 먼저 DNA 분자를 APTES(3-aminopropyltriethoxysilane) modified Si surface 위에 정렬한다. 그리고 이 기판을 농도를 달리한 pyrrole solution에서 incubationn한다. 마지막으로 APS (ammonium persulfate)와 반응시켜 conductive nanowire를 합성하였다. SEM을 이용하여 silicon 기판위에 1차원적으로 정렬된 나노 크기를 가지는 polypyrrole nanowire를 관찰할수 있었다. 그리고 pyrrole의 농도에 따라 nanowire의 uniformity를 조절할 수 있었다.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2009.05a
• /
• pp.24.2-24.2
• /
• 2009

Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.

• Korean Journal of Materials Research
• /
• v.20 no.4
• /
• pp.223-227
• /
• 2010

Recently, one-dimensional semiconducting nanomaterials have attracted considerable interest for their potential as building blocks for fabricating various nanodevices. Among these semiconducting nanomaterials,, $SnO_2$ nanostructures including nanowires, nanorods, nanobelts, and nanotubes were successfully synthesized and their electrochemical properties were evaluated. Although $SnO_2$ nanowires and nanobelts exhibit fascinating gas sensing characteristics, there are still significant difficulties in using them for device applications. The crucial problem is the alignment of the nanowires. Each nanowire should be attached on each die using arduous e-beam or photolithography, which is quite an undesirable process in terms of mass production in the current semiconductor industry. In this study, a simple process for making sensitive $SnO_2$ nanowire-based gas sensors by using a standard semiconducting fabrication process was studied. The nanowires were aligned in-situ during nanowire synthesis by thermal CVD process and a nanowire network structure between the electrodes was obtained. The $SnO_2$ nanowire network was floated upon the Si substrate by separating an Au catalyst between the electrodes. As the electric current is transported along the networks of the nanowires, not along the surface layer on the substrate, the gas sensitivities could be maximized in this networked and floated structure. By varying the nanowire density and the distance between the electrodes, several types of nanowire network were fabricated. The $NO_2$ gas sensitivity was 30~200 when the $NO_2$ concentration was 5~20ppm. The response time was ca. 30~110 sec.

• Korean Journal of Materials Research
• /
• v.20 no.12
• /
• pp.686-690
• /
• 2010

$TiO_2$ nanowires were self-catalytically synthesized on bare Si(100) substrates using metallorganic chemical vapor deposition. The nanowire formation was critically affected by growth temperature. The $TiO_2$ nanowires were grown at a high density on Si(100) at $510^{\circ}C$, which is near the complete decomposition temperature ($527^{\circ}C$) of the Ti precursor $(Ti(O-iPr)_2(dpm)_2)$. At $470^{\circ}C$, only very thin (< $0.1{\mu}m$) $TiO_2$ film was formed because the Ti precursor was not completely decomposed. When growth temperature was increased to $550^{\circ}C$ and $670^{\circ}C$, the nanowire formation was also significantly suppressed. A vaporsolid (V-S) growth mechanism excluding a liquid phase appeared to control the nanowire formation. The $TiO_2$ nanowire growth seemed to be activated by carbon, which was supplied by decomposition of the Ti precursor. The $TiO_2$ nanowire density was increased with increased growth pressure in the range of 1.2 to 10 torr. In addition, the nanowire formation was enhanced by using Au and Pt catalysts, which seem to act as catalysts for oxidation. The nanowires consisted of well-aligned ~20-30 nm size rutile and anatase nanocrystallines. This MOCVD synthesis technique is unique and efficient to self-catalytically grow $TiO_2$ nanowires, which hold significant promise for various photocatalysis and solar cell applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.04b
• /
• pp.77-78
• /
• 2009

We report numerical simulations to investigate of the dependence of the on/off current ratio and channel charge distributions in silicon nanowire (SiNW) field-effect transistors (FETs) on the channel width and thicknesses. In order to investigate the transport behavior in devices with different channel geometries, we have performed detailed two-dimensional simulations of SiNWFETs and control FETs with a fixed channel length L of 10um, but varying the channel width W from 5nm to 5um, and thickness t from 10nm to 30nm. We have shown that $Q_{ON}/Q_{OFF}$ drastically decreases (from ${\sim}2.9{\times}10^4$ to ${\sim}9.8{\times}10^3$) as the channel thickness increases (from 10nm to 30nm). As a result of the simulation using a quantum model, even higher charge density in the bottom of SiNW channel was observed than that in the bottom of control channel.

• Korean Journal of Materials Research
• /
• v.21 no.2
• /
• pp.115-119
• /
• 2011

Si Nanowire (NW) field effect transistors (FETs) were fabricated on hard Si and flexible polyimide (PI) substrates, and their electrical characteristics were compared. Si NWs used as channels were synthesized by electroless etching method at low temperature, and these NWs were refined using a centrifugation method to get the NWs to have an optimal diameter and length for FETs. The gate insulator was poly(4-vinylphenol) (PVP), prepared using a spin-coating method on the PI substrate. Gold was used as electrodes whose gap was 8 ${\mu}m$. These gold electrodes were deposited using a thermal evaporator. Current-voltage (I-V) characteristics of the device were measured using a semiconductor analyzer, HP-4145B. The electrical properties of the device were characterized through hole mobility, $I_{on}/I_{off}$ ratio and threshold voltage. The results showed that the electrical properties of the TFTs on PVP were similar to those of TFTs on $SiO_2$. The bending durability of SiNWs TFTs on PI substrate was also studied with increasing bending times. The results showed that the electrical properties were maintained until the sample was folded about 500 times. But, after more than 1000 bending tests, drain current showed a rapid decrease due to the defects caused by the roughness of the surface of the Si NWs and mismatches of the Si NWs with electrodes.

• Korean Journal of Materials Research
• /
• v.14 no.7
• /
• pp.482-488
• /
• 2004

$SiO_2$ nanowires were synthesized using the vapor evaporation method. Grown nanowires had a different shapes by kind of substrates. Diameters and lengths of the nanowires increased with increasing growth temperature and time. Mean diameters and lengths of $SiO_2$ nanowire were different by kind of substrates. These variations were attributed to nanowire densities on the substrates. The kind of substrates affected microstructure and PL properties of grown nanowires. In case of $Al_{2}O_3$ and quartz substrates, additional $O_2$ were supported during growth stages, and made a nucleation site. Therefore relative narrow nanowire was grown on $Al_{2}O_3$ and quartz substrates. Optical property were measured by photoluminescence spectroscopy. Relatively broad peak was obtained and mean peak positioned at 450 and 420nm. however in case of quartz substrates, mean peak positioned at 370nm. These peak shift was contributed to the size and substrate effects.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2003.11a
• /
• pp.116-116
• /
• 2003

Most of all nano-structures, SiC had a high electrical conductivity and mechanical strengths ay high temperatures. So It was considered a useful materials for nanosized device materials and added materials for strength hardening. Much methods were developed for SiC nanowire and nanorods like CVD, carbothermal reduction, Laser ablation and CNT-confined reduction. These methods used the VLS (Vapor-Liquid-Solid) growth mechanism. In these experiments, SiC nanowire was grown by SLS (Sold-Liquid-Solid) growth mechanism used Graphite substrate, And we characterized its microstructure to compare with VLS growth mechanism.

• Advances in nano research
• /
• v.3 no.1
• /
• pp.49-54
• /
• 2015

The structure represents symmetrical metal electrode (gate 1) - front $SiO_2$ layer - n-Si nanowire FET - buried $SiO_2$ layer - metal electrode (gate 2). At the symmetrical gate voltages high conductive regions near the gate 1 - front $SiO_2$ and gate 2 - buried $SiO_2$ interfaces correspondingly, and low conductive region in the central region of the NW are formed. Possibilities of applications of nanosize FETs at the deep inversion and depletion as a distributed capacitance are demonstrated. Capacity density is an order to ${\sim}{\mu}F/cm^2$. The charge density, it distribution and capacity value in the nanowire can be controlled by a small changes in the gate voltages. at the non-symmetrical gate voltages high conductive regions will move to corresponding interfaces and low conductive region will modulate non-symmetrically. In this case source-drain current of the FET will redistributed and change current way. This gives opportunity to investigate surface and bulk transport processes in the nanosize inversion channel.