• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.10
• /
• pp.173-184
• /
• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• Journal of Electrical Engineering and Technology
• /
• v.11 no.2
• /
• pp.416-424
• /
• 2016

In this study, automatic detection of stator winding inter-turn short circuit fault (SWISCFs) in surface-mounted permanent magnet synchronous motors (SPMSMs) and automatic classification of fault severity via a pattern recognition system (PRS) are presented. In the case of a stator short circuit fault, performance losses become an important issue for SPMSMs. To detect stator winding short circuit faults automatically and to estimate the severity of the fault, an artificial neural network (ANN)-based PRS was used. It was found that the amplitude of the third harmonic of the current was the most distinctive characteristic for detecting the short circuit fault ratio of the SPMSM. To validate the proposed method, both simulation results and experimental results are presented.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.6
• /
• pp.2326-2333
• /
• 2015

Stator turn faults in permanent magnet synchronous motors (PMSMs) are more dangerous than those in induction motors (IMs) because of the presence of spinning rotor magnets that can be turned off at will. Condition monitoring and fault detection and diagnosis of the PMSM have been receiving a growing amount of attention among scientists and engineers in the past few years. The aim of this study is to propose a new detection technique of stator winding faults in a three-phase PMSM. This technique is based on the image analysis and recognition of the stator current Concordia patterns, and will allow the identification of turn faults in the stator winding as well as its correspondent fault index severity. A test bench of a vector controlled PMSM motor behaviors under short circuited turn in two phases stator windings has been built. Some experimental results of the phase to phase short circuits have been performed for diagnosis purpose.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.4
• /
• pp.1614-1622
• /
• 2018

The research related to fault diagnosis in permanent magnet synchronous motors (PMSMs) has attracted considerable attention in recent years because various faults such as permanent magnet demagnetization and short-circuited turns can occur and result in unexpected failure of motor related system. Several conventional current and back electromotive force (BEMF) analysis techniques were proposed to detect certain faults in PMSMs; however, they generally deal with a single fault only. On the contrary, cases of multiple faults are common in PMSMs. We propose a fault diagnosis method for PMSMs with single and multiple combined faults. Our method uses three phase BEMF voltages based on the fast Fourier transform (FFT), support vector machine(SVM), and visualization tools for identifying fault types and severities in PMSMs. Principal component analysis (PCA) and t-distributed stochastic neighbor embedding (t-SNE) are used to visualize the high-dimensional data into two-dimensional space. Experimental results show good visualization performance and high classification accuracy to identify fault types and severities for single and multiple faults in PMSMs.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.14 no.5
• /
• pp.423-430
• /
• 2009

Recently as the inactive response characteristics of the existing RCD used on low voltage power distribution system, so control of overload and electric short circuit faults, major causes of electrical fires, are not enough. Therefore, this paper confirms the unreliability of the existing RCD by electrical fault simulator and proposes a EFDPD by using semiconductor switching devices and a high precision current sensor (namely, reed switch) for the prevention of electrical disasters in low voltage power distribution system caused by overload or electric short circuit faults. The sensitive reed switch in the proposed EFDPD exactly detects the increased magnetic flux with the overload or the short current caused by a number of electrical faults, and the following, the self circuit breaker in EFDPD rapidly cuts off the system. The proposed EFDPD confirms the excellent characteristics in response velocity and accuracy in comparison with the conventional circuit breaker through various operation performance analysis. The proposed EFDPD can also prevent electrical disasters, like as electrical fires, which resulted from the malfunction and inactive response characteristics of the existing RCD.

• Proceedings of the KIEE Conference
• /
• 2007.04c
• /
• pp.150-152
• /
• 2007

The stator faults yield asymmetrical operation of induction machines, such as irregular current, torque pulsation, increased losses and decreased average torque. So it is necessary to detect the stator faults and develope the monitoring system for detecting faults including vibration and noise. This paper describes the method to analysis the induction motors with the stator winding inter-turn short for investigation of the asymmetrical operation during normal and transient states. And a simple method is used for the simulation and analysis of the induction machines with stator asymmetries. Finally, simulation results, finite element analysis and experimental ones are presented. The results can be useful for real-time on-line monitoring of an induction motor.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.63-71
• /
• 2003

IDDQ testing is indispensable in improving Duality and reliability of CMOS VLSI circuits. But the major problem of IDDQ testing is slow testing speed due to time-consuming IDDQ current measurement. So one requirement is to reduce the number of target faults or to make the test sets compact in fault model. In this paper, we consider equivalent fault collapsing for transistor short faults, a fault model often used in IDDQ testing and propose an efficient algorithm for reducing the number of faults that need to be considered by equivalent fault collapsing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method.

• Journal of international Conference on Electrical Machines and Systems
• /
• v.3 no.2
• /
• pp.190-199
• /
• 2014

In the last years, fault problem in power electronics has been more and more investigated both from theoretical and practical point of view. The fault problem can cause equipment failure, data and economical losses. And the analyze system require to ensure fault problem and also rectify failures. The current errors on these faults are applied for identified type of faults. This paper presents technique to detection and identification faults in three-phase voltage source inverter (VSI) by using time-frequency distribution (TFD). TFD capable represent time frequency representation (TFR) in temporal and spectral information. Based on TFR, signal parameters are calculated such as instantaneous average current, instantaneous root mean square current, instantaneous fundamental root mean square current and, instantaneous total current waveform distortion. From on results, the detection of VSI faults could be determined based on characteristic of parameter estimation. And also concluded that the fault detection is capable of identifying the type of inverter fault and can reduce cost maintenance.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.62 no.6
• /
• pp.876-880
• /
• 2013

The major causes of electrical fire are classified to short circuit fault, overload fault, electric leakage and electric contact failure. The principal factor of the fire is electric arc or spark accompanied with such electric faults. Earth Leakage Circuit Breaker (ELB) and Molded_case Circuit Breaker (MCCB), that is, Residual Current Protective Devices (RCDs) used on low voltage distribution lines cut off earth leakage and overload, but the RCD can not cut off electric arc or spark to be a major factor of electrical fire. As the RCDs which are applied in low voltage distribution panel are prescribed to rated breaking time about 30[ms] (KS C 4613), the RCDs can't perceive to the periodic electric arc or spark of more short wavelength level. To improve such problems, this paper studies on an arc fault circuit interrupter (AFCI) using the distorted voltage wave in electric arc faults. The proposed voltage sensing type AFCI is an electrical fire prevention apparatus of new conception that operates a circuit breaker with sensing the instantaneous voltage drop of line voltage at electrical faults occurrence. The proposed AFCI is composed of control circuit topology using some semiconductor switching devices. Some experimental tests of the proposed AFCI confirm practicality and the validity of the analytical results.

• Journal of information and communication convergence engineering
• /
• v.3 no.1
• /
• pp.28-32
• /
• 2005

In this paper, we propose a novel test method to effectively detect hard and soft faults in CMOS 2-stage op-amps. The proposed method uses a very high frequency sinusoidal signal that exceeds unit gain bandwidth to maximize the fault effects. Since the proposed test method doesn't require any complex algorithms to generate the test pattern and uses only a single test pattern to detect all target faults, therefore test costs can be much reduced. The area overhead is also very small because the CUT is converted to a unit gain amplifier. Using HSPICE simulation, the results indicated a high degree of fault coverage for hard and soft faults in CMOS 2-stage op-amps. To verify this proposed method, we fabricated a CMOS op-amp that contained various short and open faults through the Hyundai 0.65-um 2-poly 2-metal CMOS process. Experimental results for the fabricated chip have shown that the proposed test method can effectively detect hard and soft faults in CMOS op-amps.