• 전자공학회논문지A
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• 제31A권10호
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• Journal of Electrical Engineering and Technology
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• 제11권2호
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• pp.416-424
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• 2016

In this study, automatic detection of stator winding inter-turn short circuit fault (SWISCFs) in surface-mounted permanent magnet synchronous motors (SPMSMs) and automatic classification of fault severity via a pattern recognition system (PRS) are presented. In the case of a stator short circuit fault, performance losses become an important issue for SPMSMs. To detect stator winding short circuit faults automatically and to estimate the severity of the fault, an artificial neural network (ANN)-based PRS was used. It was found that the amplitude of the third harmonic of the current was the most distinctive characteristic for detecting the short circuit fault ratio of the SPMSM. To validate the proposed method, both simulation results and experimental results are presented.

• Journal of Electrical Engineering and Technology
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• 제10권6호
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• pp.2326-2333
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• 2015

Stator turn faults in permanent magnet synchronous motors (PMSMs) are more dangerous than those in induction motors (IMs) because of the presence of spinning rotor magnets that can be turned off at will. Condition monitoring and fault detection and diagnosis of the PMSM have been receiving a growing amount of attention among scientists and engineers in the past few years. The aim of this study is to propose a new detection technique of stator winding faults in a three-phase PMSM. This technique is based on the image analysis and recognition of the stator current Concordia patterns, and will allow the identification of turn faults in the stator winding as well as its correspondent fault index severity. A test bench of a vector controlled PMSM motor behaviors under short circuited turn in two phases stator windings has been built. Some experimental results of the phase to phase short circuits have been performed for diagnosis purpose.

• Journal of Electrical Engineering and Technology
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• 제13권4호
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• pp.1614-1622
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• 2018

The research related to fault diagnosis in permanent magnet synchronous motors (PMSMs) has attracted considerable attention in recent years because various faults such as permanent magnet demagnetization and short-circuited turns can occur and result in unexpected failure of motor related system. Several conventional current and back electromotive force (BEMF) analysis techniques were proposed to detect certain faults in PMSMs; however, they generally deal with a single fault only. On the contrary, cases of multiple faults are common in PMSMs. We propose a fault diagnosis method for PMSMs with single and multiple combined faults. Our method uses three phase BEMF voltages based on the fast Fourier transform (FFT), support vector machine(SVM), and visualization tools for identifying fault types and severities in PMSMs. Principal component analysis (PCA) and t-distributed stochastic neighbor embedding (t-SNE) are used to visualize the high-dimensional data into two-dimensional space. Experimental results show good visualization performance and high classification accuracy to identify fault types and severities for single and multiple faults in PMSMs.

• 전력전자학회논문지
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• 제14권5호
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• pp.423-430
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• 2009

최근 저압 배전계통에서 사용되고 있는 과부하겸용 누전차단기 즉, RCD의 저조한 응답특성으로 인한 전기화재 원인의 대부분을 차지하는 단락사고 및 과부하사고에 대한 대응이 매우 미흡한 실정이다. 이에 본 논문에서는 기존 RCD에 대한 모의 사고실험을 통하여 그 비신뢰성을 확인하고, 이러한 RCD의 단점을 개선하고자 내구성과 속응성이 우수한 반도체 스위칭 소자들과 고정밀 전류센서를 이용한 "전기화재 방재장치(EFDPD : Electrical Fire Disaster Prevention Device)"를 제안하여 저압 배전계통에서의 단락 및 과부하사고로 인한 전기재해를 방지하고자 한다. 제안한 장치의 고정밀 전류센서로 사용된 리드스위치는 각종 전기사고에서 수반되는 단락전류 및 과전류에 의한 배전선로의 상승된 자속을 정밀 감지한 후, 자체 차단장치를 동작시키는 원리를 가진다. 다양한 동작특성 분석을 통하여 기존의 차단기와 비교하여 차단동작 응답속도와 그 신뢰성이 입증된다. 이로써 제안한 전기안전 제어장치는 기존 RCD들의 빈번한 오동작과 비신뢰성, 저조한 응답특성으로 인한 각종 전기사고 및 전기화재의 발생을 방지하고자 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.150-152
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• 2007

The stator faults yield asymmetrical operation of induction machines, such as irregular current, torque pulsation, increased losses and decreased average torque. So it is necessary to detect the stator faults and develope the monitoring system for detecting faults including vibration and noise. This paper describes the method to analysis the induction motors with the stator winding inter-turn short for investigation of the asymmetrical operation during normal and transient states. And a simple method is used for the simulation and analysis of the induction machines with stator asymmetries. Finally, simulation results, finite element analysis and experimental ones are presented. The results can be useful for real-time on-line monitoring of an induction motor.

• 대한전자공학회논문지SD
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• 제40권12호
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• pp.63-71
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• 2003

IDDQ 테스팅은 CMOS VLSI 회로의 품질 및 신뢰성 향상에 중요한 테스트 방식이다. 그러나 상대적으로 느린 IDDQ 테스트를 위해서는 고려한 고장 모델에서 발생 가능한 고장의 수를 감소하거나 가능한 적은 수의 테스트 패턴을 유지하는 게 필요하다. 본 논문에서는 IDDQ 테스팅에 자주 이용되는 트랜지스터 합선 고장 모델에서 발생 가능한 고장의 수를 효과적으로 감소시킬 수 있는 효율적인 등가 고장 중첩 알고리즘을 제안한다. ISCAS 벤치마크 회로의 모의 실험을 통하여 제안된 방식의 우수한 성능을 확인하였다.

• Journal of international Conference on Electrical Machines and Systems
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• 제3권2호
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• pp.190-199
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• 2014

In the last years, fault problem in power electronics has been more and more investigated both from theoretical and practical point of view. The fault problem can cause equipment failure, data and economical losses. And the analyze system require to ensure fault problem and also rectify failures. The current errors on these faults are applied for identified type of faults. This paper presents technique to detection and identification faults in three-phase voltage source inverter (VSI) by using time-frequency distribution (TFD). TFD capable represent time frequency representation (TFR) in temporal and spectral information. Based on TFR, signal parameters are calculated such as instantaneous average current, instantaneous root mean square current, instantaneous fundamental root mean square current and, instantaneous total current waveform distortion. From on results, the detection of VSI faults could be determined based on characteristic of parameter estimation. And also concluded that the fault detection is capable of identifying the type of inverter fault and can reduce cost maintenance.

• 전기학회논문지
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• 제62권6호
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• pp.876-880
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• 2013

The major causes of electrical fire are classified to short circuit fault, overload fault, electric leakage and electric contact failure. The principal factor of the fire is electric arc or spark accompanied with such electric faults. Earth Leakage Circuit Breaker (ELB) and Molded_case Circuit Breaker (MCCB), that is, Residual Current Protective Devices (RCDs) used on low voltage distribution lines cut off earth leakage and overload, but the RCD can not cut off electric arc or spark to be a major factor of electrical fire. As the RCDs which are applied in low voltage distribution panel are prescribed to rated breaking time about 30[ms] (KS C 4613), the RCDs can't perceive to the periodic electric arc or spark of more short wavelength level. To improve such problems, this paper studies on an arc fault circuit interrupter (AFCI) using the distorted voltage wave in electric arc faults. The proposed voltage sensing type AFCI is an electrical fire prevention apparatus of new conception that operates a circuit breaker with sensing the instantaneous voltage drop of line voltage at electrical faults occurrence. The proposed AFCI is composed of control circuit topology using some semiconductor switching devices. Some experimental tests of the proposed AFCI confirm practicality and the validity of the analytical results.

• Journal of information and communication convergence engineering
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• 제3권1호
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• pp.28-32
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• 2005

In this paper, we propose a novel test method to effectively detect hard and soft faults in CMOS 2-stage op-amps. The proposed method uses a very high frequency sinusoidal signal that exceeds unit gain bandwidth to maximize the fault effects. Since the proposed test method doesn't require any complex algorithms to generate the test pattern and uses only a single test pattern to detect all target faults, therefore test costs can be much reduced. The area overhead is also very small because the CUT is converted to a unit gain amplifier. Using HSPICE simulation, the results indicated a high degree of fault coverage for hard and soft faults in CMOS 2-stage op-amps. To verify this proposed method, we fabricated a CMOS op-amp that contained various short and open faults through the Hyundai 0.65-um 2-poly 2-metal CMOS process. Experimental results for the fabricated chip have shown that the proposed test method can effectively detect hard and soft faults in CMOS op-amps.