• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.127-138
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• 2013

The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.572-578
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• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.479-485
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• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.2000-2006
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• 2011

In this paper, the drain induced barrier lowering(DIBL) for doping distribution in the channel has been analyzed for double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studing because of adventages to be able to reduce the short channel effects(SCEs) to occur in convensional MOSFET. DIBL is SCE known as reduction of threshold voltage due to variation of energy band by high drain voltage. This DIBL has been analyzed for structural parameter and variation of channel doping profile for DGMOSFET. For this object, The analytical model of Poisson equation has been derived from Gaussian doping distribution for DGMOSFET. To verify potential and DIBL models based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and DIBL for DGMOSFET has been investigated using this models.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.182-189
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• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).