• Title/Summary/Keyword: Shift algorithm

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Velocity Estimation of Moving Targets by Azimuth Differentials of SAR Images (SAR 영상의 Azimuth 차분을 이용한 움직이는 물체의 속도측정방법)

  • Park, Jeong-Won;Jung, Hyung-Sup;Won, Joong-Sun
    • Korean Journal of Remote Sensing
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    • v.24 no.2
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    • pp.91-98
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    • 2008
  • We present an efficient and robust technique to estimate the velocity of moving targets from a single SAR image. In SAR images, azimuth image shift is a well blown phenomenon, which is observed in moving targets having slant-range velocity. Most methods estimated the velocity of moving targets from the distance difference between the road and moving targets or between ship and the ship wake. However, the methods could not be always applied to moving targets because it is difficult to find the road and the ship wake. We propose a method for estimating the velocity of moving targets from azimuth differentials of range-compressed image. This method is based on a phenomenon that Doppler center frequency shift of moving target causes a phase difference in azimuth differential values. The phase difference is linearly distorted by Doppler rate due to the geometry of SAR image. The linear distortion is eliminated from phase removal procedure, and then the constant phase difference is estimated. Finally, range velocity estimates for moving targets are retrieved from the constant phase difference. This technique was tested using an ENVISAT ASAR image in which several unknown ships are presented. In the case of a isolated target, the result was nearly coincident with the result from conventional method. However, in the case of a target which is located near non-target material, the difference of the result between from our algorithm and from conventional method was more than 1m/s.

Method of Walking Surface Identification Technique for Automatic Change of Walking Mode of Intelligent Bionic Leg (지능형 의족의 보행모드 자동변경을 위한 보행노면 판별 기법)

  • Yoo, Seong-Bong;Lim, Young-Kwang;Eom, Su-Hong;Lee, Eung-Hyuk
    • Journal of rehabilitation welfare engineering & assistive technology
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    • v.11 no.1
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    • pp.81-89
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    • 2017
  • In this paper, we propose a gait pattern recognition method for intelligent prosthesis that enables walking in various environments of femoral amputees. The proposed gait mode changing method is a single sensor based algorithm which can discriminate gait surface and gait phase using only strain gauges sensor, and it is designed to simplify the algorithm based on multiple sensors of existing intelligent prosthesis and to reduce cost of prosthesis system. For the recognition algorithm, we analyzed characteristics of the ground reaction force generated during gait of normal person and defined gait step segmentation and gait detection condition, A gait analyzer was constructed for the gait experiment in the environment similar to the femoral amputee. The validity of the paper was verified through the defined detection conditions and fabricated instruments. The accuracy of the algorithm based on the single sensor was 95%. Based on the proposed single sensor-based algorithm, it is considered that the intelligent prosthesis system can be made inexpensive, and the user can directly grasp the state of the walking surface and shift the walking mode. It is confirmed that it is possible to change the automatic walking mode to switch the walking mode that is suitable for the walking mode.

Fast Stream Cipher AA32 for Software Implementation (소프트웨어 구현에 적합한 고속 스트림 암호 AA32)

  • Kim, Gil-Ho;Park, Chang-Soo;Kim, Jong-Nam;Cho, Gyeong-Yeon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.6B
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    • pp.954-961
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    • 2010
  • Stream cipher was worse than block cipher in terms of security, but faster in execution speed as an advantage. However, since so far there have been many algorithm researches about the execution speed of block cipher, these days, there is almost no difference between them in the execution speed of AES. Therefore an secure and fast stream cipher development is urgently needed. In this paper, we propose a 32bit output fast stream cipher, AA32, which is composed of ASR(Arithmetic Shifter Register) and simple logical operation. Proposed algorithm is a cipher algorithm which has been designed to be implemented by software easily. AA32 supports 128bit key and executes operations by word and byte unit. As Linear Feedback Sequencer, ASR 151bit is applied to AA32 and the reduction function is a very simple structure stream cipher, which consists of two major parts, using simple logical operations, instead of S-Box for a non-linear operation. The proposed stream cipher AA32 shows the result that it is faster than SSC2 and Salsa20 and satisfied with the security required for these days. Proposed cipher algorithm is a fast stream cipher algorithm which can be used in the field which requires wireless internet environment such as mobile phone system and real-time processing such as DRM(Digital Right Management) and limited computational environments such as WSN(Wireless Sensor Network).

A Fast Normalized Cross-Correlation Computation for WSOLA-based Speech Time-Scale Modification (WSOLA 기반의 음성 시간축 변환을 위한 고속의 정규상호상관도 계산)

  • Lim, Sangjun;Kim, Hyung Soon
    • The Journal of the Acoustical Society of Korea
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    • v.31 no.7
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    • pp.427-434
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    • 2012
  • The overlap-add technique based on waveform similarity (WSOLA) method is known to be an efficient high-quality algorithm for time scaling of speech signal. The computational load of WSOLA is concentrated on the repeated normalized cross-correlation (NCC) calculation to evaluate the similarity between two signal waveforms. To reduce the computational complexity of WSOLA, this paper proposes a fast NCC computation method, in which NCC is obtained through pre-calculated sum tables to eliminate redundancy of repeated NCC calculations in the adjacent regions. While the denominator part of NCC has much redundancy irrespective of the time-scale factor, the numerator part of NCC has less redundancy and the amount of redundancy is dependent on both the time-scale factor and optimal shift value, thereby requiring more sophisticated algorithm for fast computation. The simulation results show that the proposed method reduces about 40%, 47% and 52% of the WSOLA execution time for the time-scale compression, 2 and 3 times time-scale expansions, respectively, while maintaining exactly the same speech quality of the conventional WSOLA.

A Real-Time Embedded Speech Recognition System

  • Nam, Sang-Yep;Lee, Chun-Woo;Lee, Sang-Won;Park, In-Jung
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.690-693
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    • 2002
  • According to the growth of communication biz, embedded market rapidly developing in domestic and overseas. Embedded system can be used in various way such as wire and wireless communication equipment or information products. There are lots of developing performance applying speech recognition to embedded system, for instance, PDA, PCS, CDMA-2000 or IMT-2000. This study implement minimum memory of speech recognition engine and DB for apply real time embedded system. The implement measure of speech recognition equipment to fit on embedded system is like following. At first, DC element is removed from Input voice and then a compensation of high frequency was achieved by pre-emphasis with coefficients value, 0.97 and constitute division data as same size as 256 sample by lapped shift method. Through by Levinson - Durbin Algorithm, these data can get linear predictive coefficient and again, using Cepstrum - Transformer attain feature vectors. During HMM training, We used Baum-Welch reestimation Algorithm for each words training and can get the recognition result from executed likelihood method on each words. The used speech data is using 40 speech command data and 10 digits extracted form each 15 of male and female speaker spoken menu control command of Embedded system. Since, in many times, ARM CPU is adopted in embedded system, it's peformed porting the speech recognition engine on ARM core evaluation board. And do the recognition test with select set 1 and set 3 parameter that has good recognition rate on commander and no digit after the several tests using by 5 proposal recognition parameter sets. The recognition engine of recognition rate shows 95%, speech commander recognizer shows 96% and digits recognizer shows 94%.

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A Study on Range-Doppler Processing of Time Shifted LFM Signals based on Quasi Orthogonal Property (준 독립적 특성 기반의 시간이동 LFM 신호를 이용한 거리-도플러 처리에 대한 연구)

  • Suh, Kyoung-Whoan
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.16 no.6
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    • pp.125-133
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    • 2016
  • As one of solutions to pursue the efficient use of spectrum resource, we proposed the methodology for the co-channel multi-site radar operations with the synchronous GPS clock. The proposed algorithm, based on a quasi orthogonal property, find a candidate set of the time shifted linear frequency modulation(TSLFM) signals with the minimum acceptable level of the correlation among selected TSLFM signals. To check suggested algorithm, numerical analysis for several radars operating in the same channel with a sawtooth waveform has been performed by using range-Doppler processing for the given system parameters, and computational results are presented and examined in terms of range profile and doppler shift for a targets with velocity and distance. Simulated results have a good agreement with assumed target distance and its velocity, within the error of resolution.

VLSI Design for Motion Estimation Based on Bit-plane Matching (비트 플레인 정합에 의한 움직임 추정기의 VLSI 설계)

  • Go, Yeong-Gi;O, Hyeong-Cheol;Go, Seong-Je
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.5
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    • pp.509-517
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    • 2001
  • Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

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Performance Analysis of DMF Acquisition System in Frequency-Selective Rayleigh Fading Channel (주파수 선택적 레일리 페이딩 채널에서의 DMF 초기동기 장치의 성능분석)

  • 김성철;이연우;조춘근;박형근;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.7B
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    • pp.1351-1360
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    • 1999
  • In frequency selective channels, conventional PN code acquisition schemes are not ideal candidates. This is because they are primarily designed for the AWGN channel. In this paper, a direct-sequence spread-spectrum(DSSS) PN code acquisition system based on digital matched filtering (DMF) with automatic threshold control(ATC) algorithm is presented and analyzed with regards to probability of detection and probability of false alarm. These two important probabilities, the probability of detection ($P_D$) and the probability of false alarm ($P_{FA}$) are derived and analyzed in considering Doppler shift, sampling rate, mean acquisition time, and PN chip rate in frequency selective Rayleigh fading channel when using serial-search method as detection technique. From computer simulation results of a DMF acquisition system model, it is shown that the performance of the acquisition system using ATC algorithm is better than that of constant threshold system.

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Performance Improvement of Isolated High Voltage Full Bridge Converter Using Voltage Doubler

  • Lee, Hee-Jun;Shin, Soo-Cheol;Hong, Seok-Jin;Hyun, Seung-Wook;Lee, Jung-Hyo;Won, Chung-Yuen
    • Journal of Electrical Engineering and Technology
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    • v.9 no.6
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    • pp.2224-2236
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    • 2014
  • The performance of an isolated high voltage full bridge converter is improved using a voltage doubler. In a conventional high voltage full bridge converter, the diode of the transformer secondary voltage undergoes a voltage spike due to the leakage inductance of the transformer and the resonance occurring with the parasitic capacitance of the diode. In addition, in the phase shift control, conduction loss largely increases from the freewheeling mode because of the circulating current. The efficiency of the converter is thus reduced. However, in the proposed converter, the high voltage dual converter consists of a voltage doubler because the circulating current of the converter is reduced to increase efficiency. On the other hand, in the proposed converter, an input current is distributed when using parallel input / serial output and the output voltage can be doubled. However, the voltages in the 2 serial DC links might be unbalanced due to line impedance, passive and active components impedance, and sensor error. Considering these problems, DC injection is performed due to the complementary operations of half bridge inverters as well as the disadvantage of the unbalance in the DC link. Therefore, the serial output of the converter needs to control the balance of the algorithm. In this paper, the performance of the conventional converter is improved and a balance control algorithm is proposed for the proposed converter. Also, the system of the 1.5[kW] PCS is verified through an experiment examining the operation and stability.

Performance Enhancement of CSMA/CA MAC DCF Protocol for IEEE 802.11a Wireless LANs (IEEE 802.11a 무선 LAN에서 CSMA/CA MAC DCF 프로토콜의 성능 향상)

  • Moon, Il-Young;Roh, Jae-Sung;Cho, Sung-Joon
    • Journal of Advanced Navigation Technology
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    • v.8 no.1
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    • pp.65-72
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    • 2004
  • A basic access method using for IEEE 802.11a wireless LANs is the DCF method that is based on the CSMA/CA. But, Since IEEE 802.11 MAC layer uses original backoff algorithm (Exponential backoff method), when collision occurs, the size of contention windows increases the double size. Hence, packet transmission delay time increases and efficiency is decreased by original backoff scheme. In this paper, we have analyzed TCP packet transmission time of IEEE 802.11 MAC DCF protocol for wireless LANs using a proposed enhanced backoff algorithm. From the results, in OFDM/quadrature phase shift keying channel (QPSK), we can achieve that the transmission time in wireless channel decreases as the TCP packet size increases and based on the data collected, we can infer the correlation between TCP packet size and total message transmission time, allowing for an inference of the optimal packet size in the TCP layer.

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