• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.11
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• pp.2703-2708
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• 2014

The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus transaction cycle, the wait cycle and the priority are primarily considered. In this paper, we propose the arbitration method that considers the wait cycle. Furthermore, we verify the bus transaction cycle and the wait cycle compared with the other arbitration methods through TLM(Transaction Level Model).

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.12
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• pp.716-725
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• 2004

It is extremely important to minimize network access time in constructing a high-performance PC cluster system. For PC cluster systems, it is possible to reduce network access time by maintaining network cache in each cluster node. This paper presents a Network Cache Coherent NUMA (NCC-NUMA) system to utilize network cache by locating shared memory on the PCI bus, and the NCC-NUMA card which is core module of the NCC-NUMA system is developed. The NCC-NUMA card is directly plugged into the PCI slot of each node, and contains shared memory, network cache, shared memory control module and network control module. The network cache is maintained for the shared memory on the PCI bus of cluster nodes. The coherency mechanism between the network cache and the shared memory is based on the IEEE SCI standard. According to the SPLASH-2 benchmark experiments, the NCC-NUMA system showed improvements of 56% compared with an SCI-based cluster without network cache.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.547-554
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• 2002

This paper proposes an efficient dynamic routing algorithm for Multistage Bus Networks(MBN's) in distributed shared memory environment. Our algorithm utilizes extra paths available on MBN and determines routing paths adaptively according to switch traffic in order to distribute traffic among switches. Precisely, a packet is transmitted to the next switch on an extra path having a lighter traffic. As a consequence the proposed algorithm reduces the mean response time and the average number of waiting tasks. The results of simulations, carried out with varying numbers of processors and varying switch sizes, show that the proposed algorithm improves the mean response time by 9% and the average number of waiting tasks by 21.6%, compared to the existing routing algorithms which do not consider extra paths on MBN.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2261-2266
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2009-2014
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance comparison of TDMA and Lottery bus arbitration policy developed recently due to farious conditions and propose the methods of performance improvement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1879-1884
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• 2013

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1348-1351
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• 1996

In field bus network, field device are connected with a medium. Because a medium must be shared for transmitting data, there are random delay time when data arrive destination station. It is difficult that all data packets are guaranteed synchronization and real-time restriction. In this paper, we show an algorithm that makes network utilization to maximum, guarantees real-time restriction, calculates sampling time at all control loop.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.927-936
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• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.80-86
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• 2010

The conventional bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in arbitrating the bus. The efficiency of bus usage can be determined by the selection of arbitration method. Fixed Priority, Round-Robin, TDMA and Lottery arbitration policies are studied in the conventional arbitration method where the bus priority is primarily considered. In this paper, we propose the arbitration method that calculates the bus utilization of each master. Furthermore, we verify the performance compared with the other arbitration methods through TLM(Transaction Level Model). From the results of performance verification, the arbitration methods of Fixed Priority and Round-Robin can not set the bus utilization and those of TDMA and Lottery happen the error of 50% and 70% respectively compared with bus utilization set by user in more than 100,000 cycles. On the other hand, the bandwidth-award bus arbitration method remains the error of less than 1% since approximately 1000 cycles, compared with bus utilization set by user.