• Title/Summary/Keyword: Shannon limit

Search Result 43, Processing Time 0.076 seconds

Enhancing Robustness of Information Hiding Through Low-Density Parity-Check Codes

  • Yi, Yu;Lee, Moon-Ho;Kim, Ji-Hyun;Hwang, Gi-Yean
    • Journal of Broadcast Engineering
    • /
    • v.8 no.4
    • /
    • pp.437-451
    • /
    • 2003
  • With the rapid growth of internet technologies and wide availability of multimedia computing facilities, the enforcement of multimedia copyright protection becomes an important issue. Digital watermarking is viewed as an effective way to deter content users from illegal distributions. In recent years, digital watermarking has been intensively studied to achieve this goal. However, when the watermarked media is transmitted over the channels modeled as the additive white Gaussian noise (AWGN) channel, the watermark information is often interfered by the channel noise and produces a large number of errors. So many error-correcting codes have been applied in the digital watermarking system to protect the embedded message from the disturbance of the noise, such as BCH codes, Reef-Solomon (RS) codes and Turbo codes. Recently, low-density parity-check (LDPC) codes were demonstrated as good error correcting codes achieving near Shannon limit performance and outperforming turbo codes nth low decoding complexity. In this paper, in order to mitigate the channel conditions and improve the quality of watermark, we proposed the application of LDPC codes on implementing a fairly robust digital image watermarking system. The implemented watermarking system operates in the spectrum domain where a subset of the discrete wavelet transform (DWT) coefficients is modified by the watermark without using original image during watermark extraction. The quality of watermark is evaluated by taking Into account the trade-off between the chip-rate and the rate of LDPC codes. Many simulation results are presented in this paper, these results indicate that the quality of the watermark is improved greatly and the proposed system based on LDPC codes is very robust to attacks.

Improvement in the Channel Capacity in Visible Light Emitting Diodes using Compressive Sensing (압축센싱기법을 이용한 가시광 무선링크 전송용량 증가기술 연구)

  • Jung, Eui-Suk;Lee, Yong-Tae;Han, Sang-Kook
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.15 no.10
    • /
    • pp.6296-6302
    • /
    • 2014
  • A new technique, which can increase the channel bandwidth in an optical wireless orthogonal frequency division multiplexing (OFDM) link based on a light emitting diode (LED), is proposed. The technique uses adaptive sampling to convert an OFDM signal to a sparse waveform. In compressive sensing (CS), a sparse signal that is sampled below the Nyquist/Shannon limit can be reconstructed successively with sufficient measurements. The data rate of the proposed CS-based visible light communication (VLC)-OFDM link increases from 30.72 Mb/s to 51.2 Mb/s showing an error vector magnitude (EVM) of 31 % at the quadrature phase shift keying (QPSK) symbol.

FPGA Mapping Incorporated with Multiplexer Tree Synthesis (멀티플렉서 트리 합성이 통합된 FPGA 매핑)

  • Kim, Kyosun
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.53 no.4
    • /
    • pp.37-47
    • /
    • 2016
  • The practical constraints on the commercial FPGAs which contain dedicated wide function multiplexers in their slice structure are incorporated with one of the most advanced FPGA mapping algorithms based on the AIG (And-Inverter Graph), one of the best logic representations in academia. As the first step of the mapping process, cuts are enumerated as intermediate structures. And then, the cuts which can be mapped to the multiplexers are recognized. Without any increased complexity, the delay and area of multiplexers as well as LUTs are calculated after checking the requirements for the tree construction such as symmetry and depth limit against dynamically changing mapping of neighboring nodes. Besides, the root positions of multiplexer trees are identified from the RTL code, and annotated to the AIG as AOs (Auxiliary Outputs). A new AIG embedding the multiplexer tree structures which are intentionally synthesized by Shannon expansion at the AOs, is overlapped with the optimized AIG. The lossless synthesis technique which employs FRAIG (Functionally Reduced AIG) is applied to this approach. The proposed approach and techniques are validated by implementing and applying them to two RISC processor examples, which yielded 13~30% area reduction, and up to 32% delay reduction. The research will be extended to take into account the constraints on the dedicated hardware for carry chains.