• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.336-343
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• 2018

We herein present the design and fabrication of a Rx core chip operating in the X-band (10.5~13 GHz) using Win's commercial $0.25-{\mu}m$ GaAs pHEMT process technology. The X-band core chip comprises a low-noise amplifier, a four-bit phase shifter, and a serial-to-parallel data converter. The size is $1.75mm{\times}1.75mm$, which is the state-of-the-art size. The gain and noise figure are more than 10 dB but less than 2 dB, and both the input and output return losses are less than 10 dB. The RMS phase error is less than $5^{\circ}$, and the P1dB is 2 dBm at 12.5 GHz, the performance of which is equivalent to other GaAs core chips. The fabricated core chip was packaged in a QFN package type with a size of $3mm{\times}3mm$ for the convenience of assembly. We confirmed that the performance of the packaged core chip was almost the same as that of the chip itself.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.974-977
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• 1999

In this paper, we have proposed the hardware architecture which implements the algorithm for retaining the connectivity which prevents disconnecting in the gray-scale image thinning To perform the image thinning in a real time which find a skeleton in image, it is necessary to examine the connectivity of the skeleton in a real time. The proposed architecture finds the connectivity number in the 4-clock period. The architecture is consists of three blocks, PS(Parallel to Serial) Converter and State Generator and Ridge Checker. The PS Converter changes the 3$\times$3 gray level image to four sets of image pixels. The State Generator examine the connectivity of the central pixel by searching the data from the PS Converter. the 3$\times$3 gray level image determines. The Ridge Checker determines whether the central pixel is on the skeleton or not The proposed architecture finds the connectivity of the central pixel in a 3$\times$3 gray level image in the 4-clocks. The total circuits are verified by the design tools and operate correctly.

• 한국신재생에너지학회:학술대회논문집
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• 2006.06a
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• pp.192-194
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• 2006

To elucidate possible challenges for outdoor practical use of dye-sensitized solar cells(DSC), compared with conventional Si solar cells. DSC modules still need the larger area than conventional Si solar modules to attain the same rated output because of lower photoelectron-chemical conversion efficiency. However, using batteries backup systems, the measured data shows that DSCs gathered over 12% more electricity than Si solar cells of the same rated output power in same outdoor condition. Moreover, battery charging time of DSC is about 1 hour faster than same rate of Si solar module. In this paper, 12 single DSC cells prepared for 4 serialized DSC cells was connected in 3 row parallel which have same output power rate of Si solar module. This DSC module was practiced generating characteristic experiment over outdoor daylight condition and applied with PV battery charger by using DC-DC converter. The main advantages of DSC module battery charger as compared with conventional Si solar module one are shorter charge time and lower cost.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.10 no.3
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• pp.64-70
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• 1996

In this paper, we designed a low cost data logger system using single chip microcontroller. It detects the normal and abnormal current in distribution system. A sampled analog signals are stored on RAM card(4Mbit) after digitalized by internal A/D converter. Stored data can be transmitted to the personal computer either by internal serial communication port or by external parallel communication port. The transmitted data are analyzed and displayed on personal computer.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2283-2286
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• 2003

This paper presents conservation of electrical energy in building with harmonics analysis and compensation which occur in electrical system. We use load controlling and management system in order to adjust load factor of system.The maximum demand limiting and controlling are used ,then the system can acquire the prediction and compare it to the maximum demand set point.The electrical signal analysis based on FFT technique. The harmonics are compensated by using harmonic filters.This system consists computer which works as controller, processor , analysis and database unit together with digital power meter in form of multidrop network through serial communication via RS-485.The load control system uses PLC to control load via serial communication RS-485. The A/D converter is used for sampling the electrical signals via parallel port of computer.The harmonic filters are controlled by a computer.The data of measurement such as voltage, current, power, power factor, total harmonic distortion, energy, etc., can be saved as database and analysis. The load factor is adjusted by limiting and controlling maximum demand. The load factor adjustment can reduce the cost of electric consumption and energy generation together with harmonics compensation in order to increase high efficiency of electrical system.

• Journal of the korean Society of Automotive Engineers
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• v.7 no.3
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• pp.64-73
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• 1985

In order to control ignition advance angle, this system is designed with Z-80 CPU, CTC (counter Timer Circuit), PIO(Parallel Input Output), A/D Converter and Memory, etc. Serial pulses from speed sensor and analog voltage from pressure sensor are converted to digital data. In order to reduce the error of ignition advance angle output, the reference of ignition advance angle output is set 56.25 before TDC(Top Dead Center). The table of ignition advance angle and program which have a main routine and subroutines are written into ROM ( 1 K-byte). The experimental result of this system is correspondent to the theoretical values of proposed ignition advance angle table. This system can be utilized to any other type of 4 cylinder vehicles for advance angle control by changing software.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.4
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• pp.753-758
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• 2009

Recently the high-end CMOS image sensors are developed, conforming to the SMIA CCP2 specification, which is a high-speed low-power serial interface based on LVDS technology. But this kind of technology trend makes the existing equipments are no longer useful, although their capability is still good enough to handle the recent image sensors if there was no interfacing problem. In this paper, we propose and realize a data protocol conversion system that translates the SMIA CCP2 serial signals into the existing 10-bit parallel signals. The proposed system is composed of a de-serializer and a FPCA chip, and thus can be constructed on a small PCB which enables easy integration between the existing equipments and the new high-end image sensors. Besides, the maximum transfer rate by the SMIA specification is also achieved on the implemented system. So it is expected that the implemented system can be used as a general-purpose protocol converter in a variety of sensor-related application fields.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.2
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• pp.61-69
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• 2003

In this paper, we developed the U parameter test system which inspects the property of DC parameter for semiconductor products. The developed system is interfaced by IBM-PC. It is consisted of CPLD part, ADC (Analogue to Digital Converter), DAC (Digital to Analogue Converter), voltage/current source, variable resistor and measurement part. In the proposed system, we have designed the constant voltage source and the constant current source in a part. The CPLD part is designed by VHBL, which it generates the control and converts the serial data to parallel data. The proposed system has two test channels and it operates VFCS mode and CFVS mode. The range of test voltage is from 0[V] to 100[V], and the range of test current is from 0[mA] to 100[mA)]. The diode is tested. The test results have a good performance.