• Journal of IKEEE
• /
• v.3 no.1 s.4
• /
• pp.141-149
• /
• 1999

If signal time duration of MC-CDMA method which has studied for next-generation high-speed data transmission is not sufficiently large compared to delay spread of channel, the performance is degraded by generation of intersymbol interference. In this paper, this problem will solve through serial to parallel convertor and make large sufficiently time duration of signal compared to delay spread of channel and rise variable spectral efficiency through the number of serial to parallel convertor subchannel we will add to parallel frequency diversity block for improve the performance in mobile Communication. Spectral efficiency of the proposed system is counted and compared to spectral efficiency of MC-CDMA and investigated through computer simulations by using multipath Rayleigh fading channel.

• Journal of IKEEE
• /
• v.10 no.2 s.19
• /
• pp.128-133
• /
• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.53 no.11
• /
• pp.768-775
• /
• 2004

The SSA technique in the digital circuit test is required to be repeated the input pattern stream to n bits output nodes n times in case of using a multiplexor. Because the method adopting a parallel/serial bit convertor to remove this inefficiency has disadvantage of requiring the test time n times for a pattern, the test strategy is required, which can enhance the test productivity by reducing the test time based on simplified fault detection mechanism. Accordingly, this paper proposes a test strategy which enhances the test productivity and efficiency by appling PAS (Parallel Signature Analysis) technique to those after analyzing the structure and characteristics of the digital devices including TTL and CMOS family ICs as well as ROM and RAM. The PSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Resister) representing the characteristic equation. Also, the method to obtain the optimal signature analyzer is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.23 no.4
• /
• pp.932-939
• /
• 1998

In this paper, we analyze the performance of a multicode-CDMA system which have been proposed for the multimedia communications. The performance of a multicode-CDMA system, providing good spectrum efficiency as well as serving various bit rates, is analyzed with multipath, frequency selective, slowly fading Rayleigh channel. Also the proposed scheme adopting RAKE receiver with MRC(Maximal Ratio Combine) is advantageous to multipath channel. For a practical channel modeling, the JTC(Joint Technical Committee) recommended channel model(JTC(AIR) 23-065R6) is applied to simulation. The proposed schemehas serial-to-parallel convertor which splits input data stream of 2 Mits/s into 20 branches o 100 kbits/s. From the result of simulation, the case of RAKE receiver with 3 fingers to reduce the system complexity required the relatively large $E_{b}/N_O$ of 0 dB~1.5 dB, compared to the case of RAKE receiver with the number of path finger to keep the average error rate to be $1{\times}10^{-3}$ in channel A.