• 제목/요약/키워드: Serial Number

검색결과 360건 처리시간 0.022초

Low-Quality Banknote Serial Number Recognition Based on Deep Neural Network

  • Jang, Unsoo;Suh, Kun Ha;Lee, Eui Chul
    • Journal of Information Processing Systems
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    • 제16권1호
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    • pp.224-237
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    • 2020
  • Recognition of banknote serial number is one of the important functions for intelligent banknote counter implementation and can be used for various purposes. However, the previous character recognition method is limited to use due to the font type of the banknote serial number, the variation problem by the solid status, and the recognition speed issue. In this paper, we propose an aspect ratio based character region segmentation and a convolutional neural network (CNN) based banknote serial number recognition method. In order to detect the character region, the character area is determined based on the aspect ratio of each character in the serial number candidate area after the banknote area detection and de-skewing process is performed. Then, we designed and compared four types of CNN models and determined the best model for serial number recognition. Experimental results showed that the recognition accuracy of each character was 99.85%. In addition, it was confirmed that the recognition performance is improved as a result of performing data augmentation. The banknote used in the experiment is Indian rupee, which is badly soiled and the font of characters is unusual, therefore it can be regarded to have good performance. Recognition speed was also enough to run in real time on a device that counts 800 banknotes per minute.

새로운 Bit-serial 방식의 곱셈기 및 나눗셈기 아키텍쳐 설계 (Design of a New Bit-serial Multiplier/Divier Architecture)

  • 옹수환;선우명훈
    • 전자공학회논문지C
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    • 제36C권3호
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    • pp.17-25
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    • 1999
  • 본 논문에서는 기존의 bit-serial 방식 곱셈기 및 나눗셈기의 하드웨어 부담을 줄이고 동일한 연산 사이 클 수를 갖는 새로운 bit-serial 방식의 곱셈기 및 나눗셈기 아키텍쳐를 제안한다. 제안하는 bit-serial 곱셈 및 나눗셈기 아키텍쳐는 부분곱 또는 부분나머지를 구하기 위해 레지스터 및 가감산기의 비트 수를 2배 확장하지 않기 때문에 기존의 아키텍쳐에 비해 하드웨어의 부담을 줄였다. 또한 덧셈/뺄셈과 Shift 연산을 동시에 수행하므로써 {{{{ { N}_{ } }}}} 비트 곱셈 및 나눗셈 연산에 각각 ,{{{{ { N}_{ } }}}},{{{{ { N}_{ } }}}}+ 2 사이클을 소모하며 이는 기존의 아키텍쳐와 동일한 연산 사이클 수를 지원한다. 제안하는 bit-serial 곱셈기 및 나눗셈기 아키텍쳐는 SliM Image Processor에 적용하여 실제 칩으로 구현하였으며 그 성능을 입증하였다.

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주민등록번호 변경 방법에 대한 연구 (A Study of the Change Method of Korean Resident Registration Number)

  • 이영교;안정희
    • 디지털산업정보학회논문지
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    • 제12권3호
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    • pp.65-74
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    • 2016
  • The Korean resident registration number has been used since 1962 as a personal identification number. The Korean government assigns this number to each korean citizen and it is not able to be changed. In 2000s, as the Internet was rapidly spreaded out, personal information such as the Korean resident registration number, name, home address, and phone number was leaked. The companies provide diverse internet service while collecting personal information. However, personal information was sometimes leaked because of hacking, poor information management and so on. As s results, some of citizens asked government and court of Korea to change the Korean resident registration number because they suffered material damage and emotional distress. The constitutional court decided to be able to change the number from 2018. In this study, the Korean resident registration number which is possible to change, serial number, public certificate, I-PIN, and My-PIN were analyzed comparatively. In addition, considerations when the Korean resident registration number was changed were discussed. The public certificate and I-PIN were appropriate to the case of on-line Korean resident registration number. The Korean resident registration number, serial number, My-PIN were appropriate to the case of off-line Korean resident registration number. Lastly, it would be efficient to manage the Korean resident registration number separately such as on-line and off-line.

LDPC Decoding by Failed Check Nodes for Serial Concatenated Code

  • Yu, Seog Kun;Joo, Eon Kyeong
    • ETRI Journal
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    • 제37권1호
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    • pp.54-60
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    • 2015
  • The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

Numerical discrepancy between serial and MPI parallel computations

  • Lee, Sang Bong
    • International Journal of Naval Architecture and Ocean Engineering
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    • 제8권5호
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    • pp.434-441
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    • 2016
  • Numerical simulations of 1D Burgers equation and 2D sloshing problem were carried out to study numerical discrepancy between serial and parallel computations. The numerical domain was decomposed into 2 and 4 subdomains for parallel computations with message passing interface. The numerical solution of Burgers equation disclosed that fully explicit boundary conditions used on subdomains of parallel computation was responsible for the numerical discrepancy of transient solution between serial and parallel computations. Two dimensional sloshing problems in a rectangular domain were solved using OpenFOAM. After a lapse of initial transient time sloshing patterns of water were significantly different in serial and parallel computations although the same numerical conditions were given. Based on the histograms of pressure measured at two points near the wall the statistical characteristics of numerical solution was not affected by the number of subdomains as much as the transient solution was dependent on the number of subdomains.

이진 알고리즘을 이용한 변형 시리얼테스트 설계에 관한 연구 (Design variation serial test using binary algorithm)

  • 최진석;이성주
    • 한국지능시스템학회논문지
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    • 제20권1호
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    • pp.76-80
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    • 2010
  • 급변하는 정보의 홍수 속에서 정보의 보안과 이를 가공하고 전송하는 것이 중요한 과제로 떠오르고 있다. 초기 정보보호이론과 암호화 전송단계에서는 간단한 치환과 수학적 계산 알고리즘을 적용한 암 복호화 과정을 이용하였다. 완벽한 정보보호는 One-time pad를 이용하는 것이나 이를 적용하기에는 하드웨어와 금전적 손실이 너무 크기에 실난수가 아닌 난수성을 만족하는 의사난수를 사용하고 있다. 본고에서 제안하는 변형 시리얼 테스트는 의사난수성을 입증하는 테스트 중 시리얼테스트에서 변형된 것으로 연산속도와 효율성 면에서 보다 더 강력한 난수성임을 입증하고 있다.

A new insight into design of acoustic liner arrays arrangement in the presence of a grazing flow

  • Hadi Dastourani ;Iman Bahman-Jahromi
    • Advances in Computational Design
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    • 제8권4호
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    • pp.273-293
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    • 2023
  • This study evaluated the acoustic performance of two configurations of serial HR arrays and lined HR arrays in the presence of grazing flow using a 3D numerical simulation. The dual, triple, and quad HR arrays were compared to the conventional HR array. The simulation results showed that the number of resonant frequencies increased with the number of serial HR arrays. The CTL did not significantly change with the number of serial HR arrays. The acoustic performance of the two, three, and four-lined HR arrays was compared to the conventional HR array. The results showed that the resonant frequency and TLmax increased with the number of lined HR arrays. The CTL also increased with the number of lined HR arrays. The effect of the grazing flow Mach number (Ma) was investigated on the four-lined HR array configuration and compared to the conventional HR configuration. TLmax and CTL decreased for both configurations with increasing Ma. The four-lined HR array configuration had significantly better acoustic performance than the conventional HR configuration. The TLmax and CTL increased by more than 300% when the configuration was changed from the conventional HR to the four-lined HR array at Ma = 0.The increment percentage decreased with increasing Ma.

이중적분 직렬검색을 이용한 W-CDMA 신호의 코드획득에 관한연구 (Code Acquisition of W-CDMA Signals by Double-Dwell Serial Search)

  • 김강온;차화준;전준수;김철성
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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    • pp.189-192
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    • 2000
  • In this paper, we consider a code acquisition of W-CDMA signals over multipath Rayleigh fading channel when double-dwell serial search code acquisition is used for initial synchronization. We derive the detection and false alarm probability, and mean acquisition time mathematically by taking into account of multiple H$\_$l/ cells and double-dwell serial search. It is noteworthy that the more the number of the post-detection integration, the shorter the mean acquisition time in low SNR.

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점근적 신뢰성이 있는 폐쇄직렬 생산시스템에 관한 연구 (On asymptotically reliable closed serial production systems)

  • 임종태
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 22-24 Oct. 1991
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    • pp.493-497
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    • 1991
  • A problem of analysis and design of asymptotically reliable serial production systems, closed with respect to the number of carriers that transport parts between operations, is addressed. A case study of a paint shop operation at a modern automobile assembly plant is described. The results obtained indicate that optimization of the system with respect to the number of carriers available and the capacity of the feedback buffer leads to a substantial improvement in the production rate.

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패쇄직렬 생산시스템의 점근적 성능해석 (Asymptotic performance analysis of closed serial production systems)

  • 임종태
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 26-27 Oct. 1990
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    • pp.519-522
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    • 1990
  • This paper formulates a problem of analysis and design of serial production lines, closed with respect to the number of carriers available in the system for parts transportation between operations. For two machines - two buffers systems, the paper gives an asymptotic solution and shows that optimization of the system with respect to the number of carriers available and the capacity of the feedback buffer may lead to substantial improvements of system's performance.

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