• Journal of Sensor Science and Technology
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• v.22 no.1
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• pp.89-94
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• 2013

In this paper, we developed a beam of MEMS probe card using a BeCu sheet. Silicon wafer thickness of $400{\mu}m$ was fabricated by using deep reactive ion etching (RIE) process. After forming through silicon via (TSV), the silicon wafer was bonded with BeCu sheet by soldering process. We made BeCu beam stress-free owing to removing internal stress by using joule heating. BeCu beam was fused by using joule heating caused by high current. The fabricated BeCu beam measured length of 1.75 mm and width of 0.44 mm, and thickness of $15{\mu}m$. We measured fusing current as a function of the cutting planes. Maximum current was 5.98 A at cutting plane of $150{\mu}m^2$. The proposed low-cost and simple fabrication process is applicable for producing MEMS probe beam.

• Journal of Sensor Science and Technology
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• v.24 no.4
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• pp.264-269
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• 2015

An infrared (IR) bolometer measures the change of resistance by absorbing incident IR radiation and generates a signal as a function of the radiation intensity. Since a bolometer requires temperature stabilization and light filtering except for the infrared rays, it is essential for the device to be packaged meeting conditions that above mentioned. Minimization of heat loss is needed in order to stabilize temperature of bolometer. Heat loss by conduction or convection requires a medium, so the heat loss will be minimized if the medium is a vacuum. Therefore, vacuum packaging for bolometer is necessary. Another important element in bolometer packaging is germanium (Ge) window, which transmits IR radiation to heat the bolometer. To ensure a complete transmittance of IR light, anti-reflection (AR) coatings are deposited on both sides of the window. Although the transmittance of Ge window is high for IR rays, it is difficult to use frequently in low-price IR bolometer because of its high price. In this paper, we fabricated IR window by utilizing silicon (Si) substrate instead of Ge in order to reduce the cost of bolometer packaging. To enhance the IR transmittance through Si substrate, it is textured using Reactive Ion Etching (RIE). The texturing process of Si substrate is performed along with the change of experimental conditions such as gas ratio, pressure, etching time and RF power.

• Journal of Sensor Science and Technology
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• v.29 no.4
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• pp.255-260
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• 2020

In this study, we developed a method of improving the surface-enhanced Raman spectroscopy (SERS) response characteristics by depositing a nanoporous Ag metal thin film through cluster source sputtering after forming a pyramidal texture structure on the Si substrate surface. A reactive ion etching (RIE) system with a metal mesh inside the system was used to form a pyramidal texture structure on the Si surface without following a complicated photolithography process, unlike in case of the conventional RIE system. The size of the texture structure increased with the RIE process time. However, after a process time of 60 min, the size of the structure did not increase but tended to saturate. When the RF power increased from 200 to 250 W, the size of the pyramidal texture structure increased from 0.45 to 0.8 ㎛. The SERS response characteristics were measured by depositing approximately 1.5 ㎛ of nanoporous Ag metal thin film through cluster sputtering on the formed texture structure by varying the RIE process conditions. The Raman signal strength of the nanoporous Ag metal thin film deposited on the Si substrate with the texture structure was higher than that deposited on the general silicon substrate by up to 19%. The Raman response characteristics were influenced by the pyramid size and the number of pyramids per unit area but appeared to be influenced more by the number of pyramids per unit area. Therefore, further studies are required in this regard.

• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.