• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.543-548
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• 2014

In this paper, the dielectric relaxation and reliability of high capacitance density metal-insulator-metal (MIM) capacitors using $Al_2O_3-HfO_2-Al_2O_3$ and $SiO_2-HfO_2-SiO_2$ sandwiched structure under constant voltage stress (CVS) are characterized. These results indicate that although the multilayer MIM capacitor provides high capacitance density and low dissipation factor at room temperature, it induces greater dielectric relaxation level (in ppm). It is also shown that dielectric relaxation increases and leakage current decreases as functions of stress time under CVS, because of the charge trapping effect in the high-k dielectric.

• 제어로봇시스템학회논문지
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• 제19권11호
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• pp.984-990
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• 2013

Pick and placement systems need high speeds and reliability for the position alignment process of semiconductor packages in picking up and placing them on placement trays. Image processing is usually adopted for position aligning where finding out the most suitable method is considered most important aspect of the process. This paper proposes a method for judging the performance of different image processing algorithms based on the PCI (Process Capability Index). The PCI is an index which represents the error distribution acquired from many experimental data. The bigger the index, the more reliable the results or the lower the deviation. Two compared and candidate methods are Hough Transform and PCA (Principal Component Analysis), both of which are very suitable for oblong or rectangular type packages such as BGA's. Comparing the two approaches through a CPI with enough experimental results leads to the conclusion that the PCA is much better than the Hough Transform in not only reliability, but also processing speed.

• Current Optics and Photonics
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• 제3권6호
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• pp.583-589
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• 2019

We report experimental results on 940-nm 350-mW AlGaAs/InGaAs transverse single-mode laser diodes (LDs) adopting graded-index separate confinement heterostructures (GRIN-SCH) and p,n-clad asymmetric structures, with improved temperature and small-divergence beam characteristics under high-output-power operation, for a three-dimensional (3D) motion-recognition sensor. The GRIN-SCH design provides good carrier confinement and prevents current leakage by adding a grading layer between cladding and waveguide layers. The asymmetric design, which differs in refractive-index distribution of p-n cladding layers, reduces the divergence angle at high-power operation and widens the transverse mode distribution to decrease the power density around emission facets. At an optical power of 350 mW under continuous-wave (CW) operation, Gaussian narrow far-field patterns (FFP) are measured with the full width at half maximum vertical divergence angle to be 18 degrees. A threshold current (I_th) of 65 mA, slope efficiency (SE) of 0.98 mW/mA, and operating current (I_op) of 400 mA are obtained at room temperature. Also, we could achieve catastrophic optical damage (COD) of 850 mW and long-term reliability of 60℃ with a TO-56 package.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.113-118
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• 2023

Maintenance of semiconductor equipment processes is crucial for the continuous growth of the semiconductor market. The process must always be upheld in optimal condition to ensure a smooth supply of numerous parts. Additionally, it is imperative to monitor the status of the robots that play a central role in the process. Just as many senses of organs judge a person's body condition, robots also have numerous sensors that play a role, and like human joints, they can detect the condition first in the joints, which are the driving parts of the robot. Therefore, a normal state test bed and an abnormal state test bed using an aging reducer were constructed by simulating the joint, which is the driving part of the robot. Various sensors such as vibration, torque, encoder, and temperature were attached to accurately diagnose the robot's failure, and the test bed was built with an integrated system to collect and control data simultaneously in real-time. After configuring the user screen and building a database based on the collected data, the characteristic values of normal and abnormal data were analyzed, and machine learning was performed using the KNN (K-Nearest Neighbors) machine learning algorithm. This approach yielded an impressive 94% accuracy in failure diagnosis, underscoring the reliability of both the test bed and the data it produced.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.376-376
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• 2012

Semiconductor nanowires (NWs) are future building block for nano-scale devices. Especially, Ge NWs are fascinated material due to the high electrical conductivity with high carrier mobility. It is strong candidate material for post-CMOS technology. However, thermal stability of Ge NWs are poor than conventional semiconductor material such as Si. Especially, when it reduced size as small as nano-scale it will be melted around CMOS process temperature due to the melting point depression. Recently, Graphene have been intensively interested since it has high carrier mobility with single atomic thickness. In addition, it is chemically very stable due to the $sp^2$ hybridization. Graphene films shows good protecting layer for oxidation resistance and corrosion resistance of metal surface using its chemical properties. Recently, we successfully demonstrated CVD growth of monolayer graphene using Ge catalyst. Using our growth method, we synthesized Ge/graphene core/shell (Ge@G) NW and conducted it for highly thermal stability required devices. We confirm the existence of graphene shell and morphology of NWs using SEM, TEM and Raman spectra. SEM and TEM images clearly show very thin graphene shell. We annealed NWs in vacuum at high temperature. Our results indicated that surface melting phenomena of Ge NWs due to the high surface energy from curvature of NWs start around $550^{\circ}C$ which is $270^{\circ}C$ lower than bulk melting point. When we increases annealing temperature, tip of Ge NWs start to make sphere shape in order to reduce its surface energy. On the contrary, Ge@G NWs prevent surface melting of Ge NWs and no Ge spheres generated. Furthermore, we fabricated filed emission devices using pure Ge NWs and Ge@G NWs. Compare with pure Ge NWs, graphene protected Ge NWs show enhancement of reliability. This growth approach serves a thermal stability enhancement of semiconductor NWs.

• 한국전기전자재료학회논문지
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• 제23권6호
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• pp.431-435
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• 2010

In this paper, we investigated the dependence of device performance and hot carrier lifetime on the channel direction of PMOSFET. $I_{D.sat}$ vs. $I_{Off}$ characteristic of PMOSFET with <100> channel direction is greater than that with <110> channel direction because carrier mobility of <100> channel direction is greater than that of <110> channel direction. However, hot carrier lifetime for <110> channel direction is much lower than that with <110> channel due to the greater impact ionization rate in the <100> channel direction. Therefore, concurrent consideration of reliability characteristics and device performance is necessary for channel strain engineering of MOSFETs.

• 공업화학
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• 제8권3호
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• pp.533-542
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• 1997

회로 설계의 고속화, 고성능화 경향으로 인해 반도체 봉지제의 유전특성은 회로실행과 신뢰성에 지대한 영향을 미친다. 또한 칩이 고집적화됨에 따라 신뢰성에 영향을 주는 방열성이 주요 인자가 되고 있다 결과적으로 선진적인 반도체 봉지재 제조에 있어 4가지 주요한 특성은 낮은 유전상수값, 높은 열전도도, 상대적으로 낮은 열팽창계수, 낮은 제조원가 등이다. 본 연구에서는 에폭시 봉지제의 고성능화를 위해 에폭시 모제의 충진제로서 결정성 실리카를 사용하였다 그 결과 실리카 부피량 60~70%일 때, 보다 뛰어난 물성을 갖는 반도체 봉지재를 제조할 수 있음을 확인하였다. 또한 이 실험 과정에서 반도체 봉지제의 성형조건도 설정할 수 있었다.

• ETRI Journal
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• 제39권6호
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.